AMD IP delivered with the Vivado supports synthesis using the Vivado synthesis tool only. The user logic can be synthesized using a supported third-party synthesis tools, such as Synopsys® Synplify Pro or Mentor Graphics® Precision.
The Vivado Design Suite generates a Verilog/VHDL stub file for each IP customization. Third-party synthesis tools can use this file to infer a black box for the Vivado IP.
Vivado automatically generates the stub file if it creates a synthesized DCP for the IP, as this is the tool's default behavior. It is important that the third-party synthesis tool does not insert I/O buffers for ports connected to the Vivado IP. Therefore, the <ip_name>_stub.v includes synthesis directives to prevent I/O buffer insertion.
In this lab, you use a Manage IP project to create and customize two IP used in the sample design.
- To avoid requiring access to a third-party synthesis tool, we provide you with an EDIF produced using Synplify Pro.
- Two Xilinx Design Constraints (XDC) files are also provided for constraining the design during implementation.
- An optional stage shows how to perform simulations with the IP.
- You create a netlist project and combine the IP with the netlist produced by the third-party synthesis tool.
- A script demonstrates how you use a non-project flow to bring the sources together for implementation.