Step 6: Run Synthesis - Step 6: Run Synthesis - 2026.1 English - UG939

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2026-07-15
Version
2026.1 English
For this design, there are two XDC files that are required: top_timing.xdc and top_physical.xdc.

You use one of the XDC files (top_timing.xdc), in both synthesis and implementation, while you use the other file (top_physical.xdc) only during implementation.

At this point in your Tcl script, you read the XDC file using the read_xdc command, which is used in both synthesis and implementation.

  1. Add the following to your Tcl script:
    read_xdc ../Lab_3_4_sources/Constraints/top_timing.xdc

    The design is now ready for synthesis.

    In Non-Project Mode, unlike Project Mode, there are no design runs to launch. Additionally, there is no runs infrastructure managing the strategies used and the state of the design. You manually launch the various stages of synthesis and implementation.

  2. For synthesis, you use the synth_design command. Add the following to your Tcl script:
    synth_design -top sys_integration_top

    Because you created an in-memory project and set the target part, defining the target part is not needed here. However, you must provide the top-level module name with the synth_design command.

    The various Verilog files read into the in-memory design in Step 1: Reading Design Source Files do not reference other files via an `include statement. If they did, you need to define the `include search directories with the -include_dirs option.

    After synthesis, you must generate a design checkpoint to save the results. This approach allows you to restore the synthesized design at any time without the need to rerun synthesis.

  3. Add the following write_checkpoint command to your Tcl script:
    write_checkpoint -force post_synth.dcp

    Use the -force option to overwrite the checkpoint file if it already exists.

    You can also generate any needed reports at this point, such as a post-synthesis timing summary report.

  4. Add the following line to your Tcl script:
    report_timing_summary -file timing_syn.rpt

    This command creates a comprehensive timing report for the design and writes the report to a file.