Step 2: Customize the FIFO Generator - Step 2: Customize the FIFO Generator - 2026.1 English - UG939

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2026-07-15
Version
2026.1 English
  1. From the Flow Navigator, select IP Catalog.

    The AMD IP catalog displays in a new tab.

    You can work with the IP catalog in a variety of ways. You can search using keywords in the search box or browse through the catalog in the various categories.

  2. Type fifo in the search box.

    The search results narrow the list of IP definitions displayed in the catalog.

  3. From the Memories & Storage Elements > FIFOs group select, FIFO Generator.
  4. Right-click and select Customize IP, or double-click the selected IP.

    The FIFO Generator customization window opens. There is a schematic symbol for the selected core displayed on the left. The schematic symbol changes as you customize the IP.

    Note: This is not the original setting; it shows the change that you make to the customization.
  5. Zoom into the schematic symbol using mouse strokes with the left mouse button, within the Device window.
  6. If checked, disable the Show Disabled Ports checkbox to hide unused ports on the symbol.
  7. Above the symbol, click the Documentation menu to examine the options for viewing available information.

    The Documentation menu lets you open the PDF file datasheet for the IP and open the change log to review the revision history of the core. Additionally, it allows you to open an Internet browser to navigate to the IP webpage or view any Answer Records related to the IP.

    The IP Location specifies the location to which to save the IP customization (XCI) file and any generated output products. By default, the system saves these inside the project directory structure in the project_wave_gen_ip/project_wave_gen.gen/ip directory.

    The Switch to Defaults option resets the configuration options back to the default settings.

  8. In the Customize IP dialog box, you can change the following:
    1. Component Name to char_fifo from the default name.

      The Basic tab defines the interface type, memory type, and other implementation IP options.

    2. Default Interface Type of Native.
    3. Change Fifo Implementation to Independent Clocks Block RAM.

      The customization window now looks like the previous figure.

  9. Select the Native Ports tab to set the Read Mode, Data Port Parameters, ECC, and Output Register Options, and configure Initialization.
    1. Set Read Mode to First Word Fall Through.
    2. Set the Write Width to 8 bits.

      Setting the Write Width automatically changes the Read Width to match when you click in the Read Width field.

    3. Click the Read Width field to automatically change it to 8 bits.
  10. Leave everything else with the default settings on this tab.
  11. Examine the fields of the Status Flags and Data Counts tabs.

    These fields configure other options for the FIFO Generator. For this design, leave everything with the default settings.

  12. Click OK.

    The Generate Output Products dialog box opens for you to generate required files.

  13. Leave Out of context per IP selected, and click the Generate button.
  14. Click OK.

    By default, the Vivado IDE generates the Synthesized Checkpoint (DCP) file.

    To create this DCP, you see that the Vivado tools have added an OOC module run for the char_fifo IP to the Design Runs window. The tools have also launched the run to synthesize the IP, as shown in the following figure.



    The out-of-context (OOC) run creates the DCP for the specified IP customization, which does the following:

    • Allows the IP to be complete with regard to synthesis.
    • Ensures the integrity of the core is preserved in the current design.
    • Reduces synthesis time for the top-level design in future iterations of the design flow.

    For more information on OOC runs, and the use of DCP files, refer to the Vivado Design Suite User Guide: Designing with IP (UG896).

    Important: Generate the DCP file to reduce synthesis time for the top-level design. Do not change the default synthesis setting for the IP Design Runs.
    The FIFO now appears in the Sources > IP Sources view.

  15. In the Sources window > IP Sources tab, examine the output products produced for the FIFO Generator customization. If you did not generate the output products, they automatically generate when you launch the top-level synthesis run.

    The design sources include the FIFO IP, but it has not yet been instantiated into your design. It appears at the same level as the top-level wave_gen module in the Hierarchy tab. It is located in the Block Sources folder in the Libraries and Compile Order tabs.

    The FIFO Generator customization includes instantiation templates, such as char_fifo.veo, synthesis constraints, VHDL entity and architecture definition, and Verilog simulation files. It also includes the synthesized design checkpoint (DCP).

    Note: A char_fifo.vho template also exists, but this design cannot use it.
    Note: Because the FIFO IP was originally defined in VHDL, the system adds the entity and architecture as VHDL source files. However, because Verilog is the target language for the current project, the instantiation template is a VEO file for instantiating the VHDL FIFO entity into the Verilog design. You can also customize and add IP to your design using Tcl commands.
  16. Examine the Tcl Console in the Vivado IDE, as shown in the following figure. Review the Tcl commands used to add the FIFO Generator core to your project.

    The following commands are related to the creation, customization, generation, and launch of the IP run:

    • The create_ip command adds the IP into the current project.
    • The set_property command sets the various configuration options selected in the Customize IP dialog box. Scroll up in the screen to see this command.
    • The generate_target command creates the specified output products for the customized IP. Scroll up in the screen to see this command.
    • The create_ip_run command creates the Out-of-Context synthesis run for the customized IP.
    • The launch_runs command runs synthesis on the IP customization to produce the synthesis DCP file, functional simulation netlists, and stub files for third-party synthesis tools to infer a black box for the IP.

    Refer to the Vivado Design Suite Tcl Command Reference Guide (UG835) for specific information on the different Tcl commands used in this tutorial.