In this lab, you open an AMD Vivado™ project and customize the FIFO Generator IP core. You generate the output products for the IP and instantiate it in the design RTL source. Finally, you can synthesize the project.
In this lab, you open an AMD Vivado™ project and customize the FIFO Generator IP core. You generate the output products for the IP and instantiate it in the design RTL source. Finally, you can synthesize the project.