Conclusion - Conclusion - 2026.1 English - UG939

Vivado Design Suite Tutorial: Designing with IP (UG939)

Document_ID
UG939
Release_Date
2026-07-15
Version
2026.1 English

This concludes Lab 2. You can continue examining the design, and create additional reports, or exit the AMD Vivado™ Design Suite.

In this lab, you learned to:

  • Use the Manage IP flow to browse the IP catalog and create IP customizations to store in an IP repository for later reuse. It is a convenient method for creating custom IP to share between users and projects and to manage the IP under revision control.
  • From the Manage IP Flow, you can use the customized IP in a script, either in Project or Non-Project Mode. Alternatively, you can use it from an RTL project or for inferring a black box for use with a third-party synthesis tool.
  • For convenience, Vivado also generates structural netlist Verilog/VHDL files for simulation.
  • Perform behavioral simulation with an IP or use the IP in a project. Alternatively, generate scripts for the Vivado simulator or ModelSim Simulator/Questa Advanced Simulator for standalone simulation.
  • Use other third party simulators, such as Cadence® Incisive Enterprise Simulator (IES) or Synopsys VCS MX, and Aldec where you either query both the HDL files required for simulation, and the libraries with which the files are associated, or use the export_simulation Tcl command.