This step explains how
floorplanning must be done when using the DFV. As this is a different design, with
different objects, and no timing constraints, information must be gathered in DFV and
floorplanning must be done in the parent design.
- Run the following Tcl
command:
In the device view, you again see the individual paths that you saw earlier. When you examine these more closely, you observe that some paths are crossing over each other. For this, you can alleviate the problem by updating the floorplan. The goal is to move all the items in the red box to where the green box is:show_objects [set paths [get_dataflow_paths -max_depth 1]] select_objects $paths
- In this design, there is a chain and the indices of the cells increase. Identify the first cell name in the red box and the last cell name and fill in the blanks. Zoom in within the device view and select the first cell in the chain in the red box. You should find it is the cell with the following name G_total_RAM_MULTS[3].mult_i/mult_out_reg. Repeat the process and select the final cell in the chain:G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0.
- From the above, you can conclude that you need to floorplan the following
cells:
DSPs: G_total_RAM_MULTS[3].mult_i/mult_out_reg .. G_total_RAM_MULTS[8].mult_i/mult_out_reg RAMs: G_total_RAM_MULTS[4].ram_i/ram_name_reg_bram_0 .. G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0 - You can create a single path using the following syntax, then select the
path and filter it so that only cells are
selected
The resulting output should print out the cell names that are in the path. These are also stored in the cells variable:set path [get_dataflow_paths -max_depth 11 \ -from [get_cells G_total_RAM_MULTS[3].mult_i/mult_out_reg] \ -to [get_cells G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0]] show_objects -name single $path select_objects $path select_objects [set cells [filter [get_selected_objects] {CLASS==cell}] ] puts "[join $cells \n]"G_total_RAM_MULTS[3].mult_i/mult_out_reg G_total_RAM_MULTS[4].ram_i/ram_name_reg_bram_0 G_total_RAM_MULTS[4].mult_i/mult_out_reg G_total_RAM_MULTS[5].ram_i/ram_name_reg_bram_0 G_total_RAM_MULTS[5].mult_i/mult_out_reg G_total_RAM_MULTS[6].ram_i/ram_name_reg_bram_0 G_total_RAM_MULTS[6].mult_i/mult_out_reg G_total_RAM_MULTS[7].ram_i/ram_name_reg_bram_0 G_total_RAM_MULTS[7].mult_i/mult_out_reg G_total_RAM_MULTS[8].ram_i/ram_name_reg_bram_0 G_total_RAM_MULTS[8].mult_i/mult_out_reg G_total_RAM_MULTS[9].ram_i/ram_name_reg_bram_0 - Once you have the cell names, switch designs using the switch icon at the
top of the screen. At the Tcl Console, prove that the variable still exists
after switching designs by typing the following
command:
puts “$cells” - Next, you have to delete the existing Pblocks in the design. Open the
physical constraints window and delete the Pblocks associated with the above
cells. The name is not the same but similar enough to figure out. You should
have a list like the following before deleting them:
Once you select these, right click on one and select delete.
- Next, you need to create a new Pblock with your cells. Use the following
syntax to select the cells:
select_objects $cells. Next, with the objects selected, open the Netlist window and on a selected cell, right click Draw Pblock. Ensure that Assign Selected Cells is checked and draw a Pblock anywhere in the approximate area. Click through any boxes that pop up. - At this point the Pblock is created but not saved. You can either save the constraints or you can go into the Tcl console and copy the text output and manually add this to your design constraints.