This lab uses an architected design to demonstrate some of the features of RQS. Suggestions are triggered by the design of the RTL and the placement of blocks using floor-planning. The design contains the following modules:
- Clocking Module
- The main clocking circuit for the design resides in
clocking_module.vhd. For
simplicity, RST is tied to GND. LOCKED is registered and tied to an output
port. The structure of this block is shown in the following figure.
- Reg CLKA to CLKB Module
- This module contains a synchronous CDC for a large bus. It registers input data using CLKA and then passes it to a register on the CLKB domain to be passed to the output. Registering large buses on different related clock domains can impact hold slack (WHS/THS) and setup slack (WNS/TNS).
- Bit Expander and Bit Reducer Modules
- These modules enable the expansion and contraction of internal data widths so that the design does not run out of I/Os. The modules take an arbitrary data width and expand or contract it to or from a desired size. The contraction logic creates many logic levels.
The following steps cover opening the project and examining the placement of the floor-planned modules.
- In the Tcl console, change directory to the lab directory using
the cd command as
shown
cd <extract_dir>/Lab2 - In the Tcl console type
source ./tcl/create_project.tclfile to create the project and run synthesis. You can explore the RTL files to familiarize yourself with them while synthesis is running. - In the Flow Navigator, click Open Synthesized Design.
- In the Netlist view, look at the hierarchy.
- In Device view, look at the pblock. This has been added
to control placement of the
reg_clka_to_clkbmodules and force a poor clock skew.