Step 1: Opening the Project and Understanding the Design - 2024.1 English

Vivado Design Suite Tutorial: Design Analysis and Closure Techniques (UG938)
Document ID
UG938
Release Date
2024-06-12
Version
2024.1 English

Open the following checkpoint within the folder: <extract_dir>/Lab5/part_filler_dsp_ram_routed.dcp. The design in the project is a module named part_filler_dsp_ram. This module is a chain of smaller modules that do the following:

Figure 1. Repeat n instances

The design works as follows:

  1. There is one memory in the design per DSP. Dummy data is written to and then read from this memory.
  2. The read data is registered.
  3. The registered data is squared in pipelined DSP.
  4. The bit expansion is then controlled by doing some rounding.
  5. The rounded data is registered.
  6. The registered data is written to the next instance, RAM. The chain repeats this.

The blocks highlighted in blue contain cells that are lower level cells, whilst the grey boxes contain cells that are placement drivers.

The cells are floorplanned to force the datapath to zig-zags through the part. The following image shows the floorplanning:

Figure 2. Floorplanning

By design, the floorplan is disorganized with cell placement scattered and cells not in their ideal positions. The ideal placement for this design is to locate the cells next to each other in the following order:

  1. G_total_RAM_MULTS[1].ram_i
  2. G_total_RAM_MULTS[1].mult_i
  3. G_total_RAM_MULTS[2].ram_i
  4. G_total_RAM_MULTS[2].mult_i
  5. G_total_RAM_MULTS[3].ram_i
  6. G_total_RAM_MULTS[3].mult_i

And so on upto G_total_RAM_MULTS[10].mult_i.

  1. Select some of the modules in the netlist view and explore the connectivity. In particular look at the connectivity between RAM[n] -> MULT[n] blocks and MULT[n] -> RAM[n+1]. Pay particular attention to the longer net bundles between two Pblocks further away. Alternatively, you can also open the Physical Constraints window and select each Pblock.
  2. Next, observe the connectivity between two RAMs. In the Netlist window, select the following 3 cells:
    • G_total_RAM_MULTS[1].ram_i
    • G_total_RAM_MULTS[1].mult_i
    • G_total_RAM_MULTS[2].ram_i

    • Next, right click and create a schematic

    • Next, expand the schematic to have the RAM and DSP leaf cells in view in the schematic and at least one bit of a bus connecting between cells. Allocate a brief amount of time to this task. If you encounter challenges beyond this timeframe, it is acceptable to discontinue your efforts. If successful, the results are such:

      To help you get to this point:

      1. First expand back into G_total_RAM_MULTS[1].ram_i
      2. In the DSP slice click on the following output pins
        1. A1DATA
        2. A2A1
        3. V
        4. V_DATA
        5. X
        6. ALU_OUT
        7. P
      3. Only click on D and Q pins of flops. Use the MSB of the bus when clicking through.
      4. Click on the O pin of LUTCY1

      This takes around 15 clicks to get between the two cells. It is complicated and confusing as you go through the LOOKAHEAD and the DSP slice. If you find nets looping around, ask Vivado to redraw the schematic by clicking on the Regenerate icon .

      This simple process demonstrates that tracing between cells can be complex in the standard view. Be informed, this is a simple design. Next step traces the same path in the Dataflow Viewer.