System Verilog Feature - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2024-06-12
Version
2024.1 English

AMD Vivado™ simulator now supports synthesizable as well as test bench/verification feature of System Verilog IEEE 1800-2012. In this chapter, you will go through a System Verilog example to learn about different debugging capabilities added in the Vivado simulator. You will use an IP example design provided with Vivado.