Running UVM example - 2024.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

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2024.1 English

AMD Vivado™ integrated design environment supports Universal Verification Methodology (UVM) in Vivado simulator (XSIM). UVM version 1.2 is pre-compiled and shipped with Vivado.

Through this tutorial, let us take a UVM-based example and run it in Vivado Simulator.

Note: Go to directory ug937-vivado-design-suite-tutorial-design-files/ug937-design-files/uvm of a tutorial that is downloaded at the start of Running the Simulator in Vivado IDE.