IBERT PS-GTR Flow - IBERT PS-GTR Flow - 2026.1 English - UG936

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2026-07-08
Version
2026.1 English

The IBERT PS-GTR Bring-up and subsequent EyeScan involve three different components:

  1. Generating Zynq UltraScale+ MPSoC PS Adaptive SoC & FPGA Support Archive file from the Vivado tool after configuring the PS-GTR.
  2. Using the AMD Vitis™ AMD Software Command-line Tool (XSCT) flow to generate an FSBL file using the XSA file.
  3. Using the FSBL file with Vivado Serial I/O Analyzer to bring up IBERT PS-GTR.

Tools Required

  • Vivado
  • Vitis
  • XSCT (Part of the Vitis tool)

Board/Part/Components Required

  • ZCU102 Rev 1.0 board
  • XCZU9EG-FFVB1156 production device
  • PCIe®
    • A PCIe card that has at least x4 lanes
    • PCI Express 4x Male to PCIe 16x Female Riser Cable if PCIe card is larger than x4
  • SATA
    • SanDisk 128 GB SATA SSD Drive
    • SATA connector cable
    • 4 Pin Molex to SATA Power Cable Adapter
  • USB
    • SanDisk Ultra 32 GB USB 3.0 Flash Drive
    • USB 3.0 Type A Female to Micro Male Adapter

Required Files

  • FSBL executable and linkable format file (ELF File) (Created using the following instructions), which configures the PS-GTR
  • Configuration Bitstream File (Optional file that can be needed to custom configure the FPGA depending on the board setup)
  • Tcl script to generate the FSBL and modify C-source for USB Support (when available)

Limitations

  1. FSBL should always target Cortex®-A53 processor as R5 (psu_cortexr5_0) is exclusively used by IBERT PS-GTR.
  2. Physical devices such as SATA drive, PCIe card, etc. are needed for validation.
  3. This tutorial targets the ZCU102 evaluation board. If targeting a different evaluation kit or a custom board, note the following:
    • "Run Block Automation" is only available for boards with board definition files. For custom boards, you must manually configure the processing system block including transceiver lane assignments, reference clocks, and peripheral settings based on your board schematic.
    • The GT configurations listed in this tutorial are specific to the physical lane routing of the ZCU102 board. For custom boards, valid configurations depend on your PCB design.
    • Board files are not available for custom designs.
  4. The device must be in JTAG mode and powered on.
  5. Lab 10 has only been tested with a single Zynq MPSoC in the JTAG chain.
  6. Devices that use secure boot modes have not been tested, and the Vivado IBERT GTR GUI interface does not support booting a secured device.