You can customize the IBERT core and use it to evaluate and monitor the functionality of transceivers for a variety of AMD devices. The focus of this tutorial is on AMD Kintex™ 7 GTX transceivers. Accordingly, the KC705 target board is used for this tutorial.
The following figure shows a block diagram of the interface between the IBERT Kintex 7 GTX core interfaces with Kintex 7 transceivers.
- DRP Interface and GTX Port Registers
- IBERT provides you with the flexibility to change GTX transceiver ports and attributes. Dynamic reconfiguration port (DRP) logic is included, which allows the runtime software to monitor and change any attribute in any of the GTX transceivers included in the IBERT core. When applicable, readable, and writable registers are also included. These are connected to the ports of the GTX transceiver. All are accessible at runtime using the Vivado logic analyzer.
- Pattern Generator
- Each GTX transceiver enabled in the IBERT design has a pattern generator and a pattern checker. The pattern generator sends data out through the transmitter.
- Error Detector
- Each GTX transceiver enabled in the IBERT design has a pattern generator and a pattern checker. The pattern checker takes the data through the receiver and checks it against an internally generated pattern.
Figure 1. IBERT Design Flow
