Design Description - 2025.1 English - UG936

This section has three steps as follows:

1. Creating a simple design in IP integrator that includes a System ILA and JTAG-to-AXI master.
2. Programming the AMD Kintex™ 7 FPGA KC705 Evaluation Kit Base Board and interacting with the JTAG to AXI Master IP core.
3. Using the ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction.