System Design Guide - System Design Guide - 1.0 English - UG934

AXI4-Stream Video IP and System Design Guide (UG934)

Document_ID: UG934
Release_Date: 2022-11-16
Version: 1.0 English

AXI4-Stream Video IP and System Design Guide
Introduction
AXI4-Stream Signaling Interface
READY/VALID Handshake
Start of Frame Signal
End of Line Signal
Data Format
AXI4-Stream Specific Parameterization
Encoding
Encoding Multiple Pixels - Static TDATA Configuration
Encoding Multiple Pixel - Dynamic TDATA Configuration
Example Multi Pixel Encoding
System Design Guide
Video Timing Information
Propagating Video Timing Information
Reset Requirements
Hardware Reset
Software Reset
Input/Output Interfaces - Automatic Delay Matching
Periodic Input Stream, Unconstrained Output Stream, No Frame Buffer
Output Stream Generation for Pixel Data from Frame Buffer
When Sync is Lost
When Timing Information Is Incorrect
Streaming Video Input Connection
External Frame Buffers
Incorrect Timing Information
Multipoint Interfaces
Ancillary Data
Interlaced Video Support
Interlace Video Timing
Xilinx IP Interlace Video Support
Deinterlacer
AXI4-Stream Video Bridges
AXI4-Stream to Video Out
Video In to AXI4-Stream
Frame Buffer Read/Write
Video Test Pattern Generator
Basic Video System with Interlace Content
Interlace to Progressive Conversion
Video Subsystem Software Guidelines
Video Pipeline Example
Video Subsystem Bandwidth Requirements
Bandwidth and Clocking
Live Video to/from Memory
Memory to/from Memory
Bandwidth Examples
Scaling: Down-Scaling/Decimation
Down-scaling Memory-to-Memory
Down-scaling Live External Video
Down-scaling Example System
Up-Scaling
Up-scaling Memory-to-Memory
Up-scaling Live External Video
Up-scaling Example System
Zoom
Zoom Memory-to-Memory
Zoom Live External Video
Zoom Example System
Typical Video Formats
IP Development Guide
IP Parameterization
General IP Structure
AXI4-Lite Interface
Control Register
Status and Error Registers
IRQ_ENABLE (0x000C) Register
Version (0x0010) Register
SYSDEBUG0 (0x0014) Register
SYSDEBUG1 (0x0018) Register
SYSDEBUG2 (0x001C) Register
Register Synchronization
Timing Representation
Blank/Sync Polarities
Description of Timing Variables
ACTIVE_SIZE (0x0020) Register
Frame Encoding
Input/Output Timing
Buffering Requirements
Line Buffer Placement
Buffer Management
READY – VALID Propagation
Flushing Pipelined Cores
Propagating SOF and EOL Signals
Interframe Reinitialization
Interrupt Subsystem
Debugging Features
Version Register
Core Bypass Option
Built in Test-Pattern Generator
Throughput Monitors
Tool Support
Core Generator and Vivado Compatibility
EDK Compatibility
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
Revision History
Please Read: Important Legal Notices

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