Stacked silicon interconnect (SSI) devices consist of multiple super logic regions (SLRs), joined by interposer connections called super long lines (SLLs). Paths crossing between SLRs through SLLs can present timing closure challenges.
USER_SLL_REG instructs the implementation tools to place the register in a location that is optimal for connections to the SLL. For UltraScale based architectures, this is a LAGUNA register. This is a dedicated register that drives data to, or receives data from the SLL. For Versal adaptive SoC based architectures, this selects a slice register that is adjacent to the SLL. The cells where the USER_SLL_REG property is set to true must be register cells, and should have FD/Q -> FD/D connectivity. The property can be set on either source or destination registers, or both the source and destination cells.
SLR Crossings: Partial Annotation with USER_SLL_REG
You can use the USER_SLL_REG property to guide placement of register-to-register SLR crossings so that the crossing uses SLL-accessible resources.
For best results, apply USER_SLL_REG to both the TX-side and RX-side registers of the SLR crossing. In non-DFX designs, partial annotation is also supported when the property is applied to only one side of the crossing.
- TX-Only Annotation
- When only the TX-side register has the USER_SLL_REG property, the placer
attempts to place the TX register at a site that can legally drive the SLR
crossing through an SLL.
If the corresponding RX-side SLL exits are unavailable or blocked, the placer issues a warning. For example, this can occur when LUTRAMs or other resources occupy the target slice and prevent use of the required RX-side SLL exit resources.
- RX-Only Annotation
- When only the RX-side register has the USER_SLL_REG property, the placer
attempts to place the RX register at a site that can legally receive the SLR
crossing through an SLL.
If a legal SLL-aligned placement cannot be found, the placer can leave the register in a non-optimal location and issue a warning.
- Multi-Fanout Support
- USER_SLL_REG supports one TX-side register driving up to four RX-side registers across an SLR crossing.
The following restrictions apply:
- The maximum supported RX-side fanout is four flop loads.
- All RX-side loads must be flop primitives, such as FD cells.
The property is ignored when:
- none of the nets connected to FD/D or FD/Q cross an SLR boundary,
- both nets connected to FD/D or FD/Q cross an SLR boundary,
- FD/Q net crosses an SLR boundary and has loads in two different SLRs.
For an FD cell with the USER_SLL_REG property set to false, the placer will never place the cell on a nearby LAGUNA site (hard constraint).
To further refine the placement of the registers, you can use Pblocks. In UltraScale architectures, they should include the LAGUNA sites that you can achieve using a Pblock range that includes the clock region closest to the SLR boundary. For Versal adaptive SoCs, they should be within 75 slices from the SLR boundary.
DONT_TOUCH property to registers where the
USE_SLL_REG property is set, to preserve the
corresponding flip-flops during synthesis.- Architecture Support
- All Architectures
- Applicable Objects
- Register Cells
- Value
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True(or 1): The Vivado placer will place (during detail placement) the FD cell at an optimal site, if the net connected to FD/D or FD/Q crosses an SLR boundary. -
False(or 0): Do not place the register into a LAGUNA site. This is ignored for Versal devices.
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Syntax
- Verilog Syntax
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Not applicable
- VHDL Syntax
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Not applicable
- XDC Syntax
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set_property USER_SLL_REG <True | False> <objects>XDC Example:
set_property USER_SLL_REG 1 [get_cells {cell1 cell2}]The placer will try to place cell1 and cell2 into Laguna registers at the SLR boundary.
Affected Steps
- Place Design