USER_CLOCK_VTREE_TYPE - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

The USER_CLOCK_VTREE_TYPE property is intended to help manage clock skew across a Versal stacked silicon interconnect (SSI) device. By default, the place and route tools will automatically assign a clock v-tree type to achieve the best timing characteristics for the design. The tool assigned clock v-tree is defined in the read-only CLOCK_VTREE_TYPE property. The USER_CLOCK_VTREE_TYPE property lets you manually assign a v-tree type for a clock net.

Important: The USER_CLOCK_VTREE_TYPE property can be set on a global clock net, and must only be assigned to the net segment directly driven by the global clock buffer (BUFG).

The global clock routing is handled automatically during implementation. However in cases where the USER_CLOCK_VTREE_TYPE property on a clock net has been changed after implementation, the Vivado tool might require the update_clock_routing command to properly reroute the clock nets.

Architecture Support
Versal SSI
Applicable Objects
Global clock net (get_nets) directly connected to the output of a global clock buffer except the BUFG_FABRIC
Value
The following values are available for the USER_CLOCK_VTREE_TYPE property:
  • interSLR - optimized v-tree for inter-SLR crossing performance
  • balanced - balanced skew across the height of the clock extent
  • intraSLR - skew is minimized within each SLR

Syntax

Verilog Syntax
Not applicable
VHDL Syntax
Not applicable
XDC Syntax
set_property USER_CLOCK_VTREE_TYPE <interSLR | intraSLR | balanced> <objects>

XDC Syntax Examples:

set_property USER_CLOCK_VTREE_TYPE balanced [get_nets {clk1 clk2}]
Tip: The clock net can also be defined using the global clock buffer instance, or output pin, as shown in the following example:
set_property USER_CLOCK_VTREE_TYPE balanced [get_nets -of [get_pins bufferName/O]]

Affected Steps

  • Place Design
  • Routing Design