PHYSOPT_RETIMING_FORWARD - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

The PHYSOPT_RETIMING_FORWARD attribute instructs the tool to move a register from the input of a gate and creates new registers at the output of same gate. Applying this attribute on a cell instructs the physical synthesis optimization engine (post placement step) to perform retiming.

Architecture Support
Versal
Applicable Objects
Cells (get_cells)
Values
  • True (or 1): If phys_opt_design -retime is called, the presence of the PHYSOPT_RETIMING_FORWARD property with a value of TRUE has an effect and forward retiming optimization is performed.
  • False (or 0): The Vivado logic optimization does not perform forward retiming.
XDC Synatx
set_property PHYSOPT_RETIMING_FORWARD TRUE [get_cells <cell_name> ]

Affected Steps

  • Post Place Physopt Design