PHYSOPT_RETIMING_BACKWARD - 2024.1 English

Vivado Design Suite Properties Reference Guide (UG912)

Document ID
UG912
Release Date
2024-06-05
Version
2024.1 English

The PHYSOPT_RETIMING_BACKWARD attribute instructs the tool to move a register from the output of a gate and creates new registers at the inputs of the same gate. Applying this attribute on a cell instructs the physical synthesis optimization engine (post placement step) to perform retiming.

Architecture Support
Versal
Applicable Objects
Cells (get_cells)
Values
  • True (or 1): If phys_opt_design -retime is called, the presence of the PHYSOPT_RETIMING_BACKWARD property with a value of TRUE has an effect and backward retiming optimization is performed.
  • False (or 0): The Vivado logic optimization does not perform backward retiming.
XDC Syntax
set_property PHYSOPT_RETIMING_BACKWARD TRUE [get_cells <cell_name> ]

Affected Steps

  • Post Place Physopt Design