IGNORE_BUFG_GT_CONSTRAINING is a boolean property for BUFG_GT-driven clock nets that prevents the placer from automatically constraining BUFG_GT clock loads to specific clock regions. By default, Vivado placer constrains loads of BUFG_GT-driven clocks with fanout under 10,000 to the source BUFG_GT row and within half the device width.
The user can prevent automatic BUFG_GT load constraining by setting the property IGNORE_BUFG_GT_CONSTRAINING to TRUE on the net driven by the BUFG_GT. This prevents BUFG_GT load constraining and can improve QOR for certain clocking topologies. The property is assigned to clock nets driven by a BUFG_GT global clock buffer.
- Architecture Support
- Versal adaptive SoC architectures.
- Applicable Objects
- Clock nets (get_nets) directly connected to the output of BUFG_GT global clock buffers.
- Values
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The following values are available for the IGNORE_BUFG_GT_CONSTRAINING property:
- TRUE: Automatic BUFG_GT load constraining is prevented for the clock net loads.
- FALSE: The BUFG_GT load constraining algorithm operates in the default mode (default).
Syntax
- Verilog Syntax
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Not applicable
- VHDL Syntax
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Not applicable
- XDC Syntax
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set_property IGNORE_BUFG_GT_CONSTRAINING TRUE [get_nets <clk_nets>]where <clk_nets> is a list of clock nets directly connected to the output of BUFG_GT global clock buffers.