The GCLK_DESKEW property is intended to help manage clock skew across a Versal stacked silicon interconnect (SSI) device by enabling or disabling the Calibrated Deskew feature of a clock tree. By default, the place and route tools will disable the Calibrated Deskew feature for the clock nets in the design. The GCLK_DESKEW property lets you enable or disable the Calibrated Deskew feature for a clock net.
The global clock routing is handled automatically during implementation. However, in cases where the GCLK_DESKEW property on a clock net has been changed after implementation, the Vivado tool requires unrouting the clock net, applying the new GCLK_DESKEW property value and the update_clock_routing command to properly reroute the clock nets with the new Calibrated Deskew setting.
- Architecture Support
- Versal SSI.
- Applicable Objects
- Global clock net (get_nets) directly connected to the output of a global clock buffer except the BUFG_FABRIC.
- Values
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The following values are available for the GCLK_DESKEW property:
- CALIBRATED: Enables Calibrated Deskew for a clock net.
- OFF: Disables Calibrated Deskew for a clock net.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property GCLK_DESKEW <CALIBRATED | OFF > <objects>XDC Syntax Examples:
set_property GCLK_DESKEW “CALIBRATED” [get_nets -of [get_pins bufferName/O]]
Affected Steps
- Place Design
- Route Design
See Also
- Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
- Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide