The CLOCK_ROUTE_GUIDE property defines the route of a specified clock net to a load pin in the XPIO. This property can be applied to a clock pin object. Valid values are CMT_ROW, BUFDIV_LEAF, VERTICAL_COLUMN, and ANY.
Tip: This property applies only to XPIO clock
loads.
- Architecture Support
- Versal adaptive SoC architectures.
- Values
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- CMT_ROW: The clock routing should be contained within the XPIO clock region row.
- BUFDIV_LEAF: The clock routing should pass through the BUFDIV_LEAF and the BLI.
- VERTICAL_COLUMN: The clock routing should take a vertical path to the clock root in the fabric clock region and then down to the XPIO clock region via vertical distribution.
- ANY: The clock routing can go through any permitted nodes.
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins sample_clk_mmcm/inst/clock_primitive_inst/MMCME5_inst/CLKFB1_DESKEW]
To use CLOCK_ROUTE_GUIDE, enter the constraint and assign a value based on the desired routing behavior. The currently supported values are CMT_ROW, BUFDIV_LEAF, VERTICAL_COLUMN and ANY.
Examples
To constrain the clock routing to a horizontal path contained within the XPIO bank
where the clock management tiles align in a row:
set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins myHier/myBUFG/I] To route the clock through a BUFDIV_LEAF via BLI when reaching the XPIO:
set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins myHier/myBUFG/I]