Description
For clocking purposes, each device is divided into clock regions. A CLOCK_REGION is a device object identifying an area of the AMD FPGA or device that is served by a set of clocking resources. A clock region contains configurable logic blocks (CLBs), DSP slices, block RAMs, interconnect, and associated clocking.
The number of clock regions varies with the size of the device. UltraScale devices are divided into columns and rows of segmented clock regions. These clock regions differ from previous families because they are arranged in tiles and do not span half the width of a device.
For UltraScale devices the height of a clock region is 60 CLBs, 24 DSP slices, and 12 block RAMs, with a horizontal clock spine (HCS) at its center. There are 52 I/Os per bank and four Gigabit transceivers (GTs) that are pitch matched to the clock regions.
For 7 series devices, the clock region contains 50 CLBs and one I/O bank with 50 I/Os, and a horizontal clock row (HROW) at its center.
The I/O banks in clock regions have clock capable pins that bring user clocks onto the clock routing resources within the clock region.
Refer to 7 Series FPGAs Clocking Resources User Guide (UG472) or UltraScale Architecture Clocking Resources User Guide (UG572) for more information on clock regions and the resources they contain.
Related Objects
CLOCK_REGION objects are associated with super-logic regions (SLR) on the device that the region is found in, or the TILE, SITE, or PACKAGE_BANK device objects found in the clock region. Additionally you can get the CLOCK_REGION that CELL netlist objects have been placed into.
You can query the CLOCK_REGION of an associated object with a Tcl command similar to the following, which returns the clock region that the specified cell is placed into:
get_clock_regions -of [get_cells usbEngine0/u1/u0/crc16_sum_reg[7]]In addition, you can query the SLR, TILE, SITE, BEL, and IO_BANK device objects associated with, or found in, the CLOCK_REGION. For example, the following Tcl command returns the I/O Banks in the same clock region that the specified cell is placed into:
get_iobanks -of_objects [get_clock_regions -of \
[get_cells usbEngine0/u1/u0/crc16_sum_reg[7]]]Properties
You can use the report_property command to report the properties of
a CLOCK_REGION. Refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835) for more
information.
The properties on the clock_region object include the following, with example values:
Property Type Read-only Visible Value
BOTTOM_RIGHT_TILE string true true NULL_X116Y105
CLASS string true true clock_region
COLUMN_INDEX int true true 1
FULL_NAME string true true CLOCKREGION_X1Y2
NAME string true true X1Y2
NUM_SITES int true true 1418
ROW_INDEX int true true 2
TOP_LEFT_TILE string true true CLBLL_L_X26Y149
To report the properties for a specific CLOCK_REGION, you can copy and paste the following command into the Vivado Design Suite Tcl shell or Tcl Console:
report_property -all [get_clock_regions <name>]Where <name> is the name of the clock region to
report.