CLOCK_LOW_FANOUT is a boolean property that can be assigned to clocks that have a small number of loads and that should be contained in a specific clock region. The property is assigned to clock nets driven by a global clock buffer or a set of registers driven by a global clock buffer.
When CLOCK_LOW_FANOUT is TRUE on a clock net driven by a global clock buffer, the loads should be contained within a limited number of clock regions (for Versal) or within a single clock region (for UltraScale+/UltraScale++). A load is defined as any leaf input pin on the clock network, not only the sequential clock pins. For example, LUT pins are counted as loads. If there are too many loads on the net, the Vivado tool will return a warning and ignore the CLOCK_LOW_FANOUT property.
For UltraScale, UltraScale+ architectures, when CLOCK_LOW_FANOUT is TRUE on a set of reisters driven by a BUFGCE global clock buffer, the BUFGCE global clock buffer will be replicated and will only drive the registers with this setting. The registers are placed in a single clock region and driven by global clock resources.
For Versal adaptive SoC architectures, when CLOCK_LOW_FANOUT is TRUE, regions of the loads for the BUFG driver are found as following:
- For XPIO/X5PIO drivers, the CLOCK_LOW_FANOUT clock regions are determined by the driver XPIO/X5PIO clock region of the BUFG clock​. Fabric clock regions are those which have BLI connections to that driver BUFG XPIO clock region and can be more than one clock region (1-3 Clock Regions).
- If there is an HSR load driven from the HSR route, the load is excluded. If the HSR load is driven through BLI, the load cannot be excluded.
- If any of the BLI driven XPIO loads that have BLI drivers outside of the CLOCK_LOW_FANOUT regions result in the CLOCK_LOW_FANOUT constraint being ignored.
The CLOCK_LOW_FANOUT property can conflict with other clock or placement properties. For instance, if CLOCK_DEDICATED_ROUTE is specified on the same net with any value other than TRUE, the CLOCK_DEDICATED_ROUTE property takes precedence and CLOCK_LOW_FANOUT is ignored with a warning, CLOCK_DELAY_GROUP will take precedence over CLOCK_LOW_FANOUT if all of the members of the CLOCK_DELAY_GROUP cannot be placed in a single clock region. USER_CLOCK_ROOT, LOC, and PBLOCK properties can also create conflicts with the CLOCK_LOW_FANOUT property. In each of these cases, CLOCK_LOW_FANOUT is ignored and a warning is returned.
- Architecture Support
- UltraScale, UltraScale+, and Versal adaptive SoC architectures.
- Applicable Objects
-
- Clock nets (
get_nets) connected to the output of global clock buffers that should be constrained to a single clock region. - Register cells (
get_cells) connected to the output of a BUFGCE global clock buffer. A new BUFGCE global clock buffer is replicated in parallel with the existing BUFGCE global clock buffer and the loads of the new BUFGCE global clock buffer are constrained to a single clock region.
- Clock nets (
- Value
-
-
TRUE: The clock is a low fanout net and should be constrained to a single clock region. -
FALSE: The clock is not a low fanout signal, or should not be constrained to a single clock region (default).
-
Syntax
- Verilog Syntax
-
Not applicable
- VHDL Syntax
-
Not applicable
- XDC Syntax
-
set_property CLOCK_LOW_FANOUT TRUE [get_nets <clk_nets>] set_property CLOCK_LOW_FANOUT TRUE [get_cells <ff_cells>]Where
-
<clk_nets>is a list of clock nets directly connected to the output of global clock buffers. -
<ff_cells>is a list of register cells directly connected to the output of a BUFGCE global clock buffer. (Only applies to UltraScale and UltraScale+)
-
XDC Syntax Example:
# Define a clock group to reduce skew between the nets.
set_property CLOCK_LOW_FANOUT TRUE [get_nets -of [get_pins block/myBufg/O]]
# Define a list of Registers to be driven by a separate BUFGCE and placed
in a single clock region
set_property CLOCK_LOW_FANOUT TRUE [get_cells block/myStartupCircuit/
startup_reg[*]]
Affected Steps
- Opt Design
- Place Design
- report_drc