Description
Typically a BEL, or Basic Element, corresponds to leaf-cell in the netlist view of the design. BELs are device objects on the target AMD FPGA on which to place, or map, basic netlist objects like flip-flops, LUTs, and carry logic.
BELs are grouped together on the device in SITE objects, such as SLICEs and IO Blocks (IOBs). One or more BELs can be located in a single SITE, and you can use the BEL to assign logic from the design netlist into specific locations or device resources on the target device.
There are a number of different bel types available on the different AMD FPGAs. The following are the types of bels found on the AMD Kintex™ 7 part, xc7k70tfbg676. The different TYPEs of BELs are enumerated below:
AFF AFF2
BFF BFF2
BITSLICE_CONTROL_BEL
BSCAN1 BSCAN2 BSCAN3 BSCAN4 BSCAN_BSCAN
BUFCE_BUFCE BUFCE_BUFCE_LEAF BUFCE_BUFCE_ROW
BUFFER
BUFGCE_DIV_BUFGCE_DIV BUFGCTRL_BUFGCTRL BUFG_GT_BUFG_GT BUFG_GT_BUFG_GT_SYNC
BUFHCE_BUFHCE BUFIO_BUFIO BUFMRCE_BUFMRCE BUFR_BUFR
CAPTURE_CAPTURE
CARRY4 CARRY8
CFF CFF2
CFG_IO_ACCESS
DCIRESET DCIRESET_DCIRESET
DFF DFF2
DNA_PORT DNA_PORT_DNA_PORT
DSP48E1_DSP48E1 DSP_ALU DSP_A_B_DATA DSP_C_DATA DSP_MULTIPLIER DSP_M_DATA
DSP_OUTPUT DSP_PREADD DSP_PREADD_DATA
EFF EFF2
EFUSE_USR EFUSE_USR_EFUSE_USR
F7MUX F8MUX F9MUX
FFF FFF2 FF_INIT
FIFO18E1_FIFO18E1
FRAME_ECC FRAME_ECC_FRAME_ECC GCLK_DELAY
GFF GFF2 GTHE3_CHANNEL_GTHE3_CHANNEL
GTHE3_CHANNEL_IPAD1 GTHE3_CHANNEL_IPAD2 GTHE3_CHANNEL_OPAD1 GTHE3_CHANNEL_OPAD2 GTHE3_COMMON_GTHE3_COMMON GTHE3_COMMON_PADN GTHE3_COMMON_PADP
GTXE2_CHANNEL_GTXE2_CHANNEL GTXE2_COMMON_GTXE2_COMMON HARD0 HARD1
HARD_SYNC_SYNC_UNIT HFF HFF2
HPIOBDIFFINBUF_DIFFINBUF HPIOBDIFFOUTBUF_DIFFOUTBUF HPIOB_IBUFCTRL
HPIOB_INBUF HPIOB_OUTBUF HPIOB_PAD HPIOB_PULL HPIO_OUTINV HPIO_VREF
HRIODIFFINBUF_DIFFINBUF HRIODIFFOUTBUF_DIFFOUTBUF HRIO_IBUFCTRL
HRIO_INBUF HRIO_OUTBUF HRIO_OUTINV HRIO_PAD HRIO_PULL
IBUFDS0_GTE3 IBUFDS1_GTE3 IBUFDS_GTE2_IBUFDS_GTE2 ICAP_BOT ICAP_ICAP ICAP_TOP IDELAYCTRL_IDELAYCTRL IDELAYE2_FINEDELAY_IDELAYE2_FINEDELAY IDELAYE2_IDELAYE2
ILOGICE2_IFF
ILOGICE3_IFF ILOGICE3_ZHOLD_DELAY INVERTER
IN_FIFO_IN_FIFO
IOB18M_INBUF_DCIEN IOB18M_OUTBUF_DCIEN IOB18M_TERM_OVERRIDE IOB18S_INBUF_DCIEN IOB18S_OUTBUF_DCIEN IOB18S_TERM_OVERRIDE IOB18_INBUF_DCIEN IOB18_OUTBUF_DCIEN IOB18_TERM_OVERRIDE IOB33M_INBUF_EN IOB33M_OUTBUF IOB33M_TERM_OVERRIDE IOB33S_INBUF_EN IOB33S_OUTBUF IOB33S_TERM_OVERRIDE IOB33_INBUF_EN IOB33_OUTBUF IOB33_TERM_OVERRIDE
LUT5 LUT6
LUT_OR_MEM5 LUT_OR_MEM6 MASTER_JTAG
MMCME2_ADV_MMCME2_ADV MMCME3_ADV_MMCM_TOP OBUFDS0_GTE3 OBUFDS1_GTE3 ODELAYE2_ODELAYE2
OLOGICE2_MISR OLOGICE2_OUTFF OLOGICE2_TFF OLOGICE3_MISR OLOGICE3_OUTFF OLOGICE3_TFF OUT_FIFO_OUT_FIFO
PAD
PCIE_2_1_PCIE_2_1 PCIE_3_1_PCIE_3_1 PHASER_IN_PHY_PHASER_IN_PHY PHASER_OUT_PHY_PHASER_OUT_PHY PHASER_REF_PHASER_REF
PHY_CONTROL_PHY_CONTROL
PLLE2_ADV_PLLE2_ADV PLLE3_ADV_PLL_TOP PLL_SELECT_BEL PMV2_PMV2
PULL_OR_KEEP1
RAMB18E1_RAMB18E1 RAMB18E2_U_RAMB18E2 RAMBFIFO18E2_RAMBFIFO18E2 RAMBFIFO36E1_RAMBFIFO36E1 RAMBFIFO36E2_RAMBFIFO36E2
REG_INIT RIU_OR_BEL RXTX_BITSLICE SELMUX2_1
SLICEL_A5LUT SLICEL_A6LUT SLICEL_B5LUT SLICEL_B6LUT SLICEL_C5LUT SLICEL_C6LUT SLICEL_CARRY4_AMUX SLICEL_CARRY4_AXOR SLICEL_CARRY4_BMUX SLICEL_CARRY4_BXOR SLICEL_CARRY4_CMUX SLICEL_CARRY4_CXOR SLICEL_CARRY4_DMUX SLICEL_CARRY4_DXOR
SLICEL_D5LUT SLICEL_D6LUT SLICEL_E5LUT SLICEL_E6LUT SLICEL_F5LUT SLICEL_F6LUT SLICEL_G5LUT SLICEL_G6LUT SLICEL_H5LUT SLICEL_H6LUT SLICEM_A5LUT SLICEM_A6LUT SLICEM_B5LUT SLICEM_B6LUT SLICEM_C5LUT SLICEM_C6LUT SLICEM_CARRY4_AMUX SLICEM_CARRY4_AXOR SLICEM_CARRY4_BMUX SLICEM_CARRY4_BXOR
SLICEM_CARRY4_CMUX SLICEM_CARRY4_CXOR SLICEM_CARRY4_DMUX SLICEM_CARRY4_DXOR SLICEM_D5LUT SLICEM_D6LUT SLICEM_E5LUT SLICEM_E6LUT SLICEM_F5LUT SLICEM_F6LUT SLICEM_G5LUT SLICEM_G6LUT SLICEM_H5LUT SLICEM_H6LUT
STARTUP STARTUP_STARTUP
SYSMONE1_SYSMONE1 SYSMON_IPAD1 SYSMON_IPAD2 TRISTATE_TX_BITSLICE
USR_ACCESS USR_ACCESS_USR_ACCESS XADC_XADC
XIPHY_FEEDTHROUGH_BEL
Related Objects
As seen in the figure above, leaf-level cells from the netlist design can be mapped onto bels on the target part. Bels are grouped in sites on the target AMD device, and both bels and sites are grouped into tiles and clock_regions. Each bel also has bel_pins that map to pins on the cells, and are connection points to the net netlist object.
You can query the bels of slr, tiles, sites, cells, clock_regions or nets. For example:
get_bels -of [get_clock_regions X1Y3]You can also query the cells, sites, tiles, and bel_pins of bel objects:
get_cells -of [get_bels SLICE_X104Y100/B6LUT]Properties
The properties assigned to bel objects vary by TYPE. The properties assigned to a BUFIO type of bel are as follows, with example values:
Property Type Read-only Visible Value
CLASS string true true bel
CONFIG.DELAY_BYPASS.VALUES string true true FALSE, TRUE
IS_RESERVED bool true true 0
IS_TEST bool true true 0
IS_USED bool true true 0
NAME string true true BUFIO_X0Y25/BUFIO
NUM_BIDIR int true true 0
NUM_CONFIGS int true true 1
NUM_INPUTS int true true 1
NUM_OUTPUTS int true true 1
NUM_PINS int true true 2
PROHIBIT bool false true 0
TYPE string true true BUFIO_BUFIO
The properties assigned to BEL objects vary by TYPE. To report the properties for any
of the TYPEs of BEL listed above, you can use the report_property
command:
report_property -all [lindex [get_bels -filter {TYPE == <BEL_TYPE>}] 0]Where <BEL_TYPE> should be replaced by one of the listed BEL types. For example:
report_property -all [lindex [get_bels -filter {TYPE == SLICEM_CARRY4_AXOR}] 0]
report_property -all [lindex [get_bels -filter {TYPE == LUT5}] 0]
report_property -all [lindex [get_bels -filter {TYPE == IOB33S_OUTBUF}] 0]
report_property
command returns a warning that no objects were found if there are no related objects
in the current design. Refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835) for more information on this command.