You can open the Vivado Design Suite Hardware Manager to program your design into a device. The Vivado logic analyzer and Vivado serial I/O analyzer features enable you to debug your design. For example, you can add ILA, VIO, memory IP, and JTAG-to-AXI cores to your design for debugging in the Vivado logic analyzer. You can also use the IBERT example design from the AMD IP catalog. Use it with the Vivado serial I/O analyzer to test and configure the GTs in your design.
For more information on these tools, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).