The Vivado IDE provides new users with an intuitive interface and gives advanced users the power they require. All tools and tool settings are written in native Tcl. You can run analysis and assign constraints throughout the design process. For example, the tools can provide timing or power estimations after synthesis, placement, or routing.
Because you can access the database through Tcl, you can change constraints, design configuration, or tool settings in real time. These changes often do not require re-implementation.
The Vivado IDE introduces the concept of opening designs in memory. When you open a design, the tool loads the design netlist for that stage of the flow. It assigns constraints to the design and applies the design to the target device. This lets you visualize and interact with the design at each stage.
In the Vivado IDE, you can open designs after register-transfer level (RTL) elaboration, synthesis, and implementation. You can make changes to constraints, logic, device configuration, and implementation results. You can also use design checkpoints to save the current state of any design. A design checkpoint is a snapshot of the design at any stage of the design process that includes the netlist, constraints, and implementation results.
Vivado automatically creates design checkpoints at each stage of the flow that you can open and analyze.
For more information on the Vivado IDE, refer to the Vivado Design Suite User Guide: Using the Vivado IDE (UG893). For more information on analyzing designs, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).