Using the report_dfx_summary Command - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

You can use the report_dfx_summary command to analyze DFX designs. When you run this command, the Report DFX Summary provides information on the following:

  • Design Configuration
  • Details on Reconfigurable Pblocks
  • Static and RP device utilization
  • Clock utilization of static and RP
  • Total number of PPLOC deposited during implementation and boundary pin count of each RP

The Report DFX Summary includes the following sections:

  • Design Configuration
  • Design Utilization Summary
  • Design Clock Utilization Summary
  • PPLOC Summary
  • RP Details

Design Configuration

The Design Configuration section is divided into two tables. The first table has information about the design stage, including whether the stage is a parent or child run. The static information is generated using the standard DFX flow or the Abstract Shell flow. Each RP is assigned a unique Partition ID (RP1, RP2, etc.), which is used consistently across all report tables. The second table shows details on each RP.

Figure 1. Design Configuration Table
Table 1. Design Configuration Table
Column Description
Reconfiguration Partition ID Unique ID assigned to RP
Instance Name RM cell name
Pblock Name Name of RP Pblock
Disjoint Pblock Is the RP Pblock disjoint? Yes (Y) or No (N)
# Child Pblock Number of child Pblocks under primary region for disjointed Pblocks
Sub-Child Pblock Is a sub-child Pblock present? Yes (Y) or No (N)
# Pblocks for QoR Number of child Pblocks under primary region for disjoint Pblock. Number of child Pblocks under non-disjoint Pblock with parent Pblock as an RP Pblock.
Boundary Pin Count Number of boundary pins of the RM
Number of Boundary Clocks Number of boundary clocks of the RM
Placement Footprint Number of tiles included in placement footprint of RM
Routing Footprint Number of tiles included in routing footprint of RM
Note: Child Pblocks are disjoint Pblocks with primary and secondary regions. Sub-child Pblock are child Pblocks under the primary region Pblock of a disjointed Pblock. For non-disjoint Pblocks, sub-child Pblocks are child Pblocks with the RP Pblock as the parent Pblock. .

Design Utilization Summary

The Design Utilization Summary table provides the utilization for the static domain and for each RP.

Note: For more information about design utilization, use the report_utilization Tcl command.
Table 2. RP Utilization Table
Column Description
Used Number of resources used in the Pblock
Util % Percentage of resources used out of the available resources in Pblock
Pblock Available Total resources available in the area defined by the Pblock
Pblock Avail % in Device Portion of the total device resource included in the RP Pblock
Figure 2. RP Utilization Table
Table 3. Static Utilization Table
Column Description
Used Resources used in the static domain
Util % Percentage of resources used out of the available resources in the Pblock
Static Available Total resources available for the static domain excluding the sum of all resources of all RP Pblocks from the total available device resources
Static in Device % Portion of total device resources available in the static domain
Figure 3. Static Utilization Table

Design Clock Utilization Summary

The Design Clock Utilization Summary shows the summary of global clocks used in the design. The table gives clock net names and related details. The table includes clock information for both static and dynamic domains of the design.

Note: For more information about clock usage, use the report_clock_utilization Tcl command.
Table 4. Design Clock Utilization Summary
Column Description
Clock Source Clock source in static domain or RP
Driver Type / Pin Output primitive pin that generates the clock
Driver Clock Region Device clock region where the clock source is located
Clock Expansion Window Rectangular area that includes all clock regions where clock net loads are placed
Clock Root Clock region where the clock net CLOCK_ROOT is located
Clock Period Period in nanoseconds of timing clock that propagates on the clock net
Static Load Numbers Number of static cells connected to clock driver pin
RP Load Numbers Number of RP cells connected to clock driver pin ( one column per RP)
Net Name Logical name of clock net segment connected to the clock driver pin
Figure 4. Design Clock Utilization Summary Table

PPLOC Summary

The PPLOC Summary table shows the partition pin count of each RP and the boundary pin count of each RM associated with each RP.

There can be differences in the number of partition pins between the placer and router stages. For example, if static leaf cells are placed in the expanded routing footprint, PPLOCs are not needed. These PPLOCs can be assigned by the placer but later removed by the router.

Figure 5. PPLOC Summary Table

RP Details

The RP Details tables provide information on each RP has. The name of table is based on the Reconfiguration Partition ID listed in the Design Configuration section.

Table 5. RP Details
Column Description
RM Instance name RM cell name
Parent Pblock Name of RP Pblock
# Child Pblocks Number of child Pblocks under the primary region for disjoint Pblocks
Pblock Components Number of Pblock elements in FSR and HSR. This is reported only for disjoint Pblocks.
Sub-Child Pblock Is a sub-child Pblock present? Yes (Y) or No (N)
Prohibited Site Count Number of sites prohibited by the implementation tools
Shared Tiles Count Number of tiles shared with another RP. This includes the shared clock tiles for the RM.
Overlap Tiles Count Number of overlapping tiles in routing footprint of RM. This also includes the shared tiles.
PPLOC Count Number of PPLOC at placer and router stages
PPLOC Change Reason This appears if the PPLOC is removed or modified
Figure 6. RP Details Table