MBUFG primitives in Versal devices allow leaf-level clock division to reduce clock track utilization and improve timing closure on synchronous clock domain crossings (CDCs). In earlier releases, Vivado restricted divided outputs of MBUFGCE primitives to static clock nets and internal Reconfigurable Module (RM) clock nets. You could not use these outputs on boundary clock nets in Dynamic Function eXchange (DFX) designs. The undivided O1 clock output from a static MBUFG can drive loads in one or more dynamic regions.
Vivado now supports divided outputs (O2, O3, O4) of MBUFGCE primitives as boundary clock nets, subject to the requirements in this section.
Supported Usage
The following configuration is supported:
- The MBUFGCE instance is in the Static region.
- One or more divided outputs (O2, O3, O4) drive loads within a single RM.
Required Design Methodology
- O1 Boundary Clock Connection
- You must connect the O1 output of the MBUFGCE to the RM through a hierarchical boundary pin.
- The O1 output defines the routed boundary clock net. Vivado
implements divided clocks (O2/O3/O4) using BUFDIV_LEAF resources near
the loads. Vivado derives PPLOC assignment and clock
region expansion from the O1 boundary clock net.
- Using a divided output as a boundary clock without establishing the O1
boundary connection results in the following design rule check (DRC)
error.
[DRC HDPR-154] Versal RM Interface Pin Check for MBUFG divided clocks: Reconfigurable module <RM name> has a MBUFGCE <instance> divided clock used as a boundary clock net, but the corresponding master clock (O1) is not connected to the RM boundary.
- CLRB_LEAF Signal Connection
- You must connect the CLRB_LEAF input to the RM through a hierarchical boundary pin.
- The CLRB_LEAF input on MBUFG primitives asynchronously resets the BUFDIV_LEAF divider elements. In DFX designs, you must ensure that BUFDIV_LEAF elements are reset to a known state across Static and RM regions. If the upstream clock driving the MBUFG is reset during operation, the MBUFG output clocks must also be reset to maintain synchronization.
- Although it is logically a static signal, CLRB_LEAF drives divider
elements located inside the RM. You must therefore model it as a
boundary net with explicit connectivity.
- Using a divided output as a boundary clock without establishing the
CLRB_LEAF boundary connection results in the following DRC
error.
[DRC HDPR-154] Versal RM Interface Pin Check for MBUFG divided clocks: Reconfigurable module <RM name> has a MBUFGCE <instance> divided clock as a boundary clock net, but its CLRB_LEAF driver net is not connected to the RM.
Unsupported Boundary Clock Topologies
The following configurations using MBUFGCE divided outputs as boundary clock nets are not supported:
- MBUFGCE located in RM driving boundary loads: An MBUFGCE instance within an RM
must not drive boundary clock nets or static region loads. This configuration
results in a DRC
error.
[DRC HDPR-158] Versal Illegal MBUFGxx drivers in pblock Reconfigurable module <RM name> has a MBUFGCE divided clock as a boundary clock net with MBUFGCE in RM. This is not currently supported. MBUFG divided clocks can be used as boundary clocks only when MBUFG is in static. - Use across multiple RMs: Divided outputs from a single MBUFGCE must not drive
loads in multiple RMs. This configuration results in a DRC
error.
[DRC HDPR-162] Unsupported MBUFGCE connectivity of divided clock: Static MBUFGCE <instance> with active CLRB_LEAF pin drives a divided clock with loads in multiple Reconfigurable Modules. This will cause unintended clock resets. Please ensure the divided clock output from a static MBUFGCE drives loads within a single Reconfigurable Module (RM) only. - Use across static and RM regions: Divided outputs from a single MBUFGCE must not
drive loads across Static and RM regions. This configuration results in a DRC
error.
[DRC HDPR-162] Unsupported MBUFGCE connectivity of divided clock: Static MBUFGCE <instance> with active CLRB_LEAF pin drives a divided clock with loads in static and Reconfigurable Module. This will cause unintended clock resets. Please ensure the divided clock output from a static MBUFGCE drives loads within a single Reconfigurable Module (RM) only.