USER_SLL_REG instructs the implementation tool to place the register in a location that is optimal for connections to the SLL. This is a dedicated register that drives data to, or receives data from the SLL. In DFX, the USER_SLL_REG property can be used for SLL guidance and PPLOC assignments. The cells where the USER_SLL_REG property is set to be true must be register cells and should have FD/Q → FD/D connectivity. The property should be set on both source and destination registers. For more information on USER_SLL_REG, see the Vivado Design Suite Properties Reference Guide (UG912).
The following are the use cases to show how the USER_SLL_REG is used in a DFX design:
- RM – RM path across SLR
- Static to RM path across SLR
- Abstract shell RM implementation
RM – RM Path Across SLR
In this design, source FlipFlop in SLR0 and destination FlipFlop in SLR1 are in different RMs. In parent implementation run, you must apply the USER_SLL_REG property on both cells in different SLRs to guide the optimal SLL usage. The tool applies PPLOC on the UBUMP and the LAG_OUT node.
report_route_status -of_objects [get_nets rp_slr0_dut_inst/crossing_0_1_inst/in_tx[0]]
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Route information for rp_slr0_dut_inst/crossing_0_1_inst/in_tx[0]
Route status: ROUTED
This net is fully routed
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The route tree for this net is:
Route Tree:
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Subtree: 0
[{ CLE_E_CORE_S0X97Y572/CLE_SLICEL_TOP_0_EQ2_PIN (65535)
CLE_E_CORE_S0X97Y572/CLE_SLICEL_TOP_0_EQ2 ( 0) CLE_E_CORE_S0X97Y572/CLE_E_CORE.CLE_SLICEL_TOP_0_EQ2_PIN->>CLE_SLICEL_TOP_0_EQ2
SLL2_1_S0X96Y572/BNODE_OUTS_E11 ( 6) SLL2_1_S0X96Y572/SLL2.LOGIC_OUTS_E14->>BNODE_OUTS_E11
SLL2_1_S0X96Y572/LAG_CASCOUT_TXI0 ( 1) SLL2_1_S0X96Y572/SLL2.BNODE_OUTS_E11->>LAG_CASCOUT_TXI0
p SLL2_1_S0X96Y572/UBUMP0 ( 0) SLL2_1_S0X96Y572/SLL2.LAG_CASCOUT_TXI0->>UBUMP0
p SLL2_1_S1X96Y517/LAG_OUT0 ( 0) SLL2_1_S1X96Y517/SLL2.UBUMP0->>LAG_OUT0
}] CLE_W_CORE_S1X96Y517/CLE_SLICEL_TOP_0_LAG_E1_PIN ( 0) CLE_W_CORE_S1X96Y517/CLE_W_CORE.CLE_SLICEL_TOP_0_LAG_E1->>CLE_SLICEL_TOP_0_LAG_E1_PIN
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set_property USER_SLL_REG 1 [get_cells rp_slr0_dut_inst/crossing_0_1_inst/in_rx_reg[0]]
set_property USER_SLL_REG 1 [get_cells rp_slr1_dut_inst/crossing_1_0_inst/in_tx_reg[0]]
Static to RM Path Across the SLR
In this design, the source FlipFlop is static in SLR1, and the destination FlipFlop is RM in SLR0. In the parent implementation run, you must apply the USER_SLL_REG property on both cells in different SLRs to guide the optimal SLL usage. For the RM boundary pin the tool applies the PPLOC on LAG_OUT node.
report_route_status -of_objects [get_nets design_1_i/static_1/Flipflops_1/inst/q[0]]
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Route information for design_1_i/static_1/Flipflops_1/inst/q[0]
Route status: ROUTED
This net is fully routed
------------------------------------------------------------
The route tree for this net is:
Route Tree:
------------------------------------------
Subtree: 0
[{ CLE_E_CORE_S1X69Y544/CLE_SLICEM_TOP_1_EQ2_PIN (65535)
CLE_E_CORE_S1X69Y544/CLE_SLICEM_TOP_1_EQ2 ( 0) CLE_E_CORE_S1X69Y544/CLE_E_CORE.CLE_SLICEM_TOP_1_EQ2_PIN->>CLE_SLICEM_TOP_1_EQ2
SLL2_S1X68Y544/BNODE_OUTS_W25 ( 6) SLL2_S1X68Y544/SLL2.LOGIC_OUTS_E38->>BNODE_OUTS_W25
SLL2_S1X68Y544/LAG_CASCOUT_TXI1 ( 2) SLL2_S1X68Y544/SLL2.BNODE_OUTS_W25->>LAG_CASCOUT_TXI1
SLL2_S0X68Y545/UBUMP1 ( 1) SLL2_S1X68Y544/SLL2.LAG_CASCOUT_TXI1->>UBUMP1
p SLL2_S0X68Y545/LAG_OUT1 ( 0) SLL2_S0X68Y545/SLL2.UBUMP1->>LAG_OUT1
}] CLE_W_CORE_S0X68Y545/CLE_SLICEL_TOP_0_LAG_W1_PIN ( 0) CLE_W_CORE_S0X68Y545/CLE_W_CORE.CLE_SLICEL_TOP_0_LAG_W1->>CLE_SLICEL_TOP_0_LAG_W1_PIN
------------------------------------------
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Abstract Shell RM Implementation
As explained previously, if the USER_SLL_REG property is used in the parent implementation, it must be reapplied in the abstract shell implementation only to the RM cell. If the property is not applied, the tool might not place the register in the dedicated sites that drive or are driven by the SLL node.
report_route_status -of_objects [get_nets rp_slr0_dut_inst/crossing_0_1_inst/in_tx[0]]
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Route information for rp_slr0_dut_inst/crossing_0_1_inst/in_tx[0]
Route status: ROUTED
This net is fully routed, and has locked routing nodes
------------------------------------------------------------
The route tree for this net is:
Route Tree:
------------------------------------------
Subtree: 0
[{ CLE_E_CORE_S0X97Y572/CLE_SLICEL_TOP_0_EQ2_PIN (65535)
CLE_E_CORE_S0X97Y572/CLE_SLICEL_TOP_0_EQ2 ( 0) CLE_E_CORE_S0X97Y572/CLE_E_CORE.CLE_SLICEL_TOP_0_EQ2_PIN->>CLE_SLICEL_TOP_0_EQ2
SLL2_1_S0X96Y572/BNODE_OUTS_E11 ( 6) SLL2_1_S0X96Y572/SLL2.LOGIC_OUTS_E14->>BNODE_OUTS_E11
SLL2_1_S0X96Y572/LAG_CASCOUT_TXI0 ( 1) SLL2_1_S0X96Y572/SLL2.BNODE_OUTS_E11->>LAG_CASCOUT_TXI0
* p SLL2_1_S0X96Y572/UBUMP0 ( 0) SLL2_1_S0X96Y572/SLL2.LAG_CASCOUT_TXI0->>UBUMP0
* SLL2_1_S1X96Y517/LAG_OUT0 ( 0) SLL2_1_S1X96Y517/SLL2.UBUMP0->>LAG_OUT0
* }] CLE_W_CORE_S1X96Y517/CLE_SLICEL_TOP_0_LAG_E1_PIN ( 0) CLE_W_CORE_S1X96Y517/CLE_W_CORE.CLE_SLICEL_TOP_0_LAG_E1->>CLE_SLICEL_TOP_0_LAG_E1_PIN
------------------------------------------
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The following figure illustrates the route status of an SLR crossing net after the abstract shell implementation. In this case, the USER_SLL_REG property is applied to the RM cell that drives the net, and the tool places the RM cell in the cell that directly drives the used SLL node.