- Device support: All 7 series, AMD Zynq™
, UltraScale,
UltraScale+ and
Versal devices supported by the Dynamic
Function eXchange flow.
- Source types for RMs: RTL, DCP, EDIF, XDC, XCI, XCIX.
- XCI or XCIX (AMD IP)
cannot be the top level.
- Netlist source types (EDIF) are limited to a single file
that represents the entire RM.
- Module-level constraints must be scoped to the hierarchical
instance.
- Greybox (black box module with tie-offs) implementation can be
done
- An extensive set of Design Rule Checks can be issued from within the
project environment.
- All synthesis and implementation design switches can be used.
- PR Verify is automatically called before bitstream generation for any child
configuration.