For Spartan UltraScale+ FPGAs, bitstream (.bit) files are not used. Instead, the programmable device image (PDI) file defines the application-specific FPGA functionality. The full-device PDI file contains the platform loader manager (PLM) firmware .elf for boot and configuration and the programmable logic (PL) data .rcdo (equivalent to the bitstream data). Partial images do not include the PLM firmware .elf, as it has already been loaded in the platform management controller (PMC), but the format of these partial images are also PDI files, containing the PL .rcdo data for the user-defined logical region.
When generating full and partial programming images in the Vivado
IDE, the Generate Bitstream step creates the full and partial programming images by
default, as it does for all DFX designs. However, this command is comprised of two
explicit steps: write_bitstream and bootgen. The write_bitstream step creates full and partial .bit
files, but these files must NOT be used to program the device. The outputs of Bootgen
are the desired .pdi files that are the ones to send to the Spartan
UltraScale+ device.
If you are not using the Vivado IDE in project mode, you can
generate full and partial programming images using these two explicit steps. The
write_bitstream command is used exactly as it is for any other UltraScale+ device, but instead of using
the full or partial .bit files, you need to use the .bif and
.rcdo files that are generated (along with the fixed
plm.elf delivered with Vivado). Use
bootgen with the -arch option set to
spartanup to create the necessary .pdi
files.
bootgen -arch spartanup -image <design.bif> -o <design.pdi>Repeat this command for each full or partial programming image required.