Setting Up Inserted Debug Cores - 2024.2 English - UG909

After synthesis, you can identify details about the debug features. This step is necessary for the insertion flow but not the instantiation flow. The insertion flow allows you to defer selection of which signals to probe and the customization of the ILA core itself.

After synthesis completes, open the synthesized design. This post-synthesis view of the parent run can be used for managing the DFX floorplan, because it shows the full design hierarchy for the primary configuration. With this view open, do the following:

1. In the Flow Navigator, select Set Up Debug.
   Figure 1. Set Up Debug Command
2. In the Set Up Debug dialog box, click Next.
3. In the Nets to Debug screen, adjust settings as needed, add more nets if desired, and click Next. This screen shows a list of signals that are tagged with the Debug (BD) or MARK_DEBUG (RTL) property.
   Figure 2. Set Up Debug Dialog Box Nets to Debug
4. In the ILA Core Options screen, adjust the ILA debug core settings as needed, and click Next and then Finish to complete the debug setup.
   Figure 3. Set Up Debug Dialog Box ILA Core Options

After you click Finish, the tools insert the ILA core. The core is declared, properties of the core are defined, and the core is connected to the existing design logic. This information is stored in the post-synthesis checkpoint for this configuration and in an RM-specific constraint file that is created and placed within the source set of the target RM in the Partition Definition. The generation of the ILA core itself (and the debug hub core) is actually done during the opt_design phase of implementation. In the Netlist view, these cores are still black boxes, as shown in the following figure.

In the Schematic view, these cores are represented by yellow levels of hierarchy, as shown in the following figure.

Save the design checkpoint before continuing.

This sequence of steps for the Set Up Debug command must be repeated for other configurations if reconfigurable modules not included in the parent configuration are to be debugged. For every other reconfigurable module that is expected to have ILA cores inserted, a configuration containing that RM must be opened to declare the ILA core details, if you are not using default settings. The Open Synthesized Design selection in the Flow Navigator can open any run configuration. Right-click on Open Synthesized Design and select Open DFX Configuration, followed by the desired configuration.

You can also perform this action of opening a design configuration from the Tcl Console. Open a parent or child run configuration by calling open_run directly as follows:

open_run synth_1 -name synth_1 -pr_config <configuration>

After opening the child run configuration, the process is the same. Call Set Up Debug to define the details of the ILA core and its connections, and save the modified configuration checkpoint.

Compile the parent and child runs as you would for any DFX design. Debug cores are generated during the opt_design step. You can confirm successful insertion by opening the routed checkpoints and examining the design hierarchy. Reconfigurable modules do not need to have ILA core insertion performed even if other RMs for the same RP have inserted ILA. The parent configuration is required to have debug core insertion to establish the NoC connectivity to the static design, and it is recommended that debug hubs are still added to all RMs to maintain a consistent NoC topology. Greybox configurations are supported as child configurations with the insertion flow.

Interacting with the debug cores for a DFX design, regardless of design flow, matches a standard debug solution. For more information on debug capabilities in Versal devices, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908). For an example design showing both flow methodologies, see the Versal Device DFX Debug Tutorials available from the AMD GitHub repository.