Segmented Configuration is a solution that enables you to boot the processors in a device and access DDR memory before the programmable logic (PL) is configured. This allows DDR-based software, such as Linux, to boot first, followed by the PL, which you can configure later if needed via any primary or secondary boot device or through a DDR image store. The Segmented Configuration feature is designed to provide the Versal boot sequence with flexibility similar to AMD Zynq™ UltraScale+™ MPSoCs methods of configuring the PL . This feature is optional when targeting first-generation Versal devices, but it is always enabled for second-generation Versal devices, including AMD Versal™ AI Edge Series Gen 2 and AMD Versal™ Prime Series Gen 2.
This solution uses a standard Vivado tool flow
through implementation, with the only additional annotation required being the
identification of NoC path segments to include in the initial boot image. This
identification occurs automatically after you set the project property that enables the
feature. Programming image generation (write_device_image) automatically splits the programming images into two
PDI files, which are stored and delivered separately. The entire PL is dynamic and can
be completely reloaded while any operating system and DDR memory access remain active.
Segmented Configuration is not DFX, but it can be used to meet similar goals. After your design is up and running, Segmented Configuration enables you to dynamically reload the entirety of the PL domain, similar to how you can reload a portion of the PL using DFX. When using Segmented Configuration, the dynamic region is determined by the silicon, so you do not have the ability to change the boundary between static and dynamic.
The capability within Segmented Configuration that pairs multiple PL images with a fixed boot image is referred to as PL Reload. The explicit DFX design flow is not required, and you design in separate projects. However, you must take specific steps to ensure the contents of the boot image are fixed so each new PL image can connect properly. This is done by locking and reusing the NoC solution from a golden design image. The concept is similar to DFX in that the PS boot image must remain fixed, with all details locked, including PS-PL boundary interface usage and the physical and addressing information for the NoC paths that cross between domains.
In general, supported use cases in Vivado are relatively narrow in scope. Different PL images are expected to be subtle variations of a base design, at least in terms of the boundary conditions. The initial golden design run must be a superset of all connectivity required for any PL variant that connects to this fixed boot image. All characteristics of the interface: pin usage, address apertures, NoC connectivity (number and types of connections), and so on, must not exceed this initial image. Subsets of connectivity are permitted (tie off unused ports) but you might introduce new PS-PL boundary connections.
The standard DFX solution cannot currently be used in designs that have enabled Segmented Configuration. This combination would effectively enable a two-level nested DFX solution, where the upper dynamic region is the entire PL, and the lower dynamic region is one or more traditional DFX modules. This combined solution is planned for a future Vivado release. If you have a need for this combined feature solution, contact AMD support at versal_seg_cfg_ea@amd.com.
For more information on Segmented Configuration, including design requirements and a tutorial walk-through, see the tutorial available in the AMD Vivado GitHub repository.