Segmented Configuration - 2024.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-12-13
Version
2024.2 English

Segmented configuration is a solution that enables designers to boot the processors in a Versal device and access DDR memory before the programmable logic (PL) is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can be configured later if needed via any primary or secondary boot device or through a DDR image store. The segmented configuration feature is intended to present the Versal boot sequence with similar flexibility to configure PL as can be done with AMD Zynq™ UltraScale+™ MPSoCs.

This solution uses a standard Vivado tool flow through implementation, with the only additional annotation required being the identification of NoC path segments to be included in the initial boot image. This occurs automatically after the project property enabling the feature has been set. Programming image generation (write_device_image) automatically splits the programming images into two PDI files to be stored and delivered separately. The entire PL is dynamic and can be completely reloaded while any operating system and DDR memory access remain active.

Segmented Configuration is not DFX, but can be used to meet similar goals. Once a design is up and running, Segmented Configuration enables users to dynamically reload the entirety of the PL domain, much like one can do for a portion of the PL using DFX. The dynamic region when using Segmented Configuration is based on the silicon, so users do not have the ability to change the boundary between static and dynamic.

The capability within Segmented Configuration that pairs multiple PL images with a fixed boot image is referred to as “PL Reload.” The explicit DFX design flow is not required and users will design in separate projects, but specific steps must be taken to ensure the contents of the boot image are fixed so each new PL image is able to connect properly. This is done by locking and reusing the NoC solution from a golden design image. The concept is similar to DFX in that the PS boot image must remain fixed, with all the details locked, from PS-PL boundary interface usage to physical and addressing information for the NoC paths that cross between domains.

In general, supported use cases in Vivado 2024.2 are narrow in scope. Different PL images are expected to be subtle variations of a base design, at least in terms of the boundary conditions. The initial "golden" design run must be a superset of all connectivity required for any PL variant that is to be connected to this fixed boot image, and all characteristics of the interface -- pin usage, address apertures, NoC connectivity (number and types of connections), etc. must not exceed this initial image. Subsets of connectivity are permitted (tie off unused ports) but you might not introduce new PS-PL boundary connections.

The standard DFX solution cannot yet be used in designs that have enabled Segmented Configuration. This combination will effectively enable a two-level Nested DFX solution, where the upper dynamic region is the entire PL, and the lower dynamic region is one or more traditional DFX modules. This combined solution is planned for a future Vivado release.

For more information on Segmented Configuration, including design requirements and a tutorial walk-through, see the tutorial available from the AMD Vivado GitHub repository.