When a row of clock tiles is shared between multiple RPs, it is possible that some of the sites along this row cannot be used for placement. To avoid potential unroutability because of tile splitting, the DFX flow automatically prohibits usage of certain clocking or logical resource tiles. To avoid this scenario, AMD recommends keeping a gap of at least one clock region between multiple RP Pblocks if utilization estimation meets the design need.
For example, in a multi-RP design, (with RPs RP1 and RP2), if a clock for RP2 is required to traverse through RP1 to reach loads in RP2, some block RAM sites in the traversed RP (RP1) are prohibited for use by the placer.
In this scenario some of the clock routing resources in RP1 are also
claimed by RP2 so they are shared equally. The RCLK tiles RCLK_BRAM_CLKBUF_* are part of
clock routing network and due to sharing by the 2 RPs, only the top or bottom half can
be claimed by RP1. Due to the configuration frame programming during reconfiguration,
RCLK_BRAM_CLKBUF tiles must be programmed together with all block RAM tiles in the same
half column. A critical warning is issued during opt_design for such a scenario. The prohibited sites can be viewed in the
Device View.
[Constraints 18-5689] RCLK tile RCLK_BRAM_CLKBUF_CORE_X*Y* is shared by PBLOCK RP1 (owns LSB tracks) and PBLOCK RP2 (owns MSB tracks). For the shared usage, BRAM tiles and their adjacent interface tiles at the NORTH of the shared RCLK tile are prohibited because they could not be used for placement within PBLOCK RP1.