PPLOC Summary - 2024.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-12-13
Version
2024.2 English

The PPLOC Summary table shows the partition pin count of each RP and the boundary pin count of each RM associated with each RP.

There can be differences in the number of partition pins between the placer and router stages. For example, if static leaf cells are placed in the expanded routing footprint, PPLOCs are not needed. These PPLOCs can be assigned by the placer but later removed by the router.

Figure 1. PPLOC Summary Table Generated by Your Tool