Because the reconfigurable logic is modified while the device is operating, the static logic connected to outputs of RM must ignore the data from RM during partial reconfiguration. The RMs do not provide valid output data until partial reconfiguration is complete and the reconfigured logic is initialized. It is not possible to predict or simulate the functionality of the RM. Logical decoupling isolates the dynamic part of the design from the static, ensuring no unintended activity disrupts the static design.
There are number of boundary types where logical decoupling should be inserted, based on the connectivity of the RP, and there are different strategies for each scenario. Boundaries can be within the PL, within the NoC, or at the PS-PL boundary.
At the end of partial reconfiguration a GSR event is triggered to initialize all the logic in the reconfigured region. For very large reconfigurable partitions, especially those spanning multiple super logic regions (SLR) on multi-die devices, this global set-reset can take multiple clock cycles to propagate through all the logical elements in that region. Because of this duration, it is possible that some circuitry might be released before others, potentially leading to unintended behavior. AMD recommends to employ techniques such as enabled clocks, local synchronous resets and/or safe state machines to ensure that all dynamic logic starts together and functions as intended.