A common design practice to mitigate this issue involves registering all output signals on the static side of the interface from the RP. An enable signal isolates the logic until it is completely reconfigured. Other approaches include a simple 2-to-1 MUX on each output port or higher-level bus controller functions. In addition, using clock buffers with muxes (for example, BUFGMUX) or enables (for example, BUFGCE) on clock signals entering the dynamic region allows pausing any activity driven by those static clocks while reconfiguration occurs. This prevents logic from moving on from its initial state until the reconfigurable module is completely loaded and released for operation.
Two pieces of IP are available from AMD to provide decoupling capabilities in the PL. The DFX Decoupler IP allows you to insert multiplexers to easily and efficiently decouple AXI4-Lite, AXI4-Stream, and custom interfaces. This IP disables key signals to prevent unwanted activity on the RP boundary. The DFX AXI Shutdown Manager IP provides a more intelligent way to decouple AXI interfaces, offering different responses to requests rather than holding boundaries constant. Click here for more information about the DFX Decoupler.