A common design practice to mitigate this issue is to register all output signals on the static side of the interface from the RP. An enable signal is used to isolate the logic until it is completely reconfigured. Other approaches include a simple 2-to-1 MUX on each output port or to higher level bus controller functions.
Two pieces of IP are available from AMD to provide decoupling capabilities in the PL. The DFX Decoupler IP allows you to insert multiplexers to easily and efficiently decouple AXI4-Lite, AXI4-Stream, and custom interfaces. This IP disables key signals to prevent unwanted activity on the RP boundary. The DFX AXI Shutdown Manager IP provides a more intelligent way to decouple AXI interfaces, offering different responses to requests rather than holding boundaries constant. More information about the DFX Decoupler IP is available on the Xilinx.com website.