- Engineering silicon (ES) for AMD UltraScale™ or AMD UltraScale+™ devices does not officially support Dynamic Function eXchange. To investigate the capabilities of DFX on ES devices, contact AMD support for advice.
- Do not drive multiple outputs of a single RM with the same source. Each output of an RM must have a unique driver.
- When using AMD Virtex™ UltraScale+™ VU29P devices, connections between the IBUFDS_GTM and GTM_DUAL sites might be unroutable if the placer does not place them on the same SLR and the same side of the device. You might encounter route_design Route 35-7 in this case. If this occurs, you must LOC both the IBUFDS_GTM and GTM_DUAL instances to appropriate locations in the same SLR on the same side of the device.
- AMD Versal™ DFX designs targeting SSI devices with reconfigurable partitions spanning multiple SLRs compiled in Vivado versions prior to 2025.1: glitching of static routes crossing these SLR boundaries can occur during reconfiguration. These designs should be reimplemented using Advanced Flow (in Vivado 2024.2 or newer) and all programming images (full and partial PDI) must be regenerated using Vivado 2025.1 or newer. The failure occurrence possibility is incredibly low but non-zero. For more information, see Answer Record 000036769.
- Certain AMD Versal™
DFX designs compiled in Vivado versions prior to 2025.1 might experience NoC
Compiler errors if the locked static design checkpoint is brought to Vivado 2025.1 or newer to implement new
Reconfigurable Modules. Changes in the NoC Compiler affect designs with very
specific conditions:
- Two or more Reconfigurable Partitions
- Reuse of pre-2025.1 post-synthesis or locked static checkpoints
- NoC streaming endpoints with N by M connectivity
These designs might encounter NoC DRC NOCCHK-1 or NoC compilation error Ipconfig75-4217. The issue can be avoided by resynthesizing and implementing the static design to generate results with the updated NoC Compiler (version 2025.1 or newer). For more information, see Answer Record 000039002.
- If the initial configuration of a 7 series SSI device (7V2000T, 7VX1140T) is done through an SPI interface, partial bitstreams cannot be delivered to the master (or any) ICAP; they must be delivered to an external port, such as JTAG. If the initial configuration is done through any other configuration port, the master ICAP can be used as the delivery port for partial bitstreams. Contact AMD support for a workaround.