Dynamic Function eXchange (DFX) allows for the reconfiguration of modules within an active design. This flow requires the implementation of multiple configurations, which ultimately results in full bitstreams for each configuration and partial bitstreams for each reconfigurable module (RM). The number of configurations required varies by the number of modules that need to be implemented. However, all configurations use the same top-level, or static, placement, and routing results. These static results are exported from the initial configuration and imported by all subsequent configurations using checkpoints.
DFX is a comprehensive solution with many parts. These parts include the silicon capability for dynamic reconfiguration. They also include the AMD Vivado™ software flow that compiles designs from RTL to bitstream. They also include complementary features, such as IP. In this release, there is a mix of DFX and partial reconfiguration (PR) terminology. DFX represents the overall solution, and PR represents one component technology piece within that solution.
Complementary documentation, such as application notes, white papers, and videos, does not always use DFX terminology, but all documentation from 2020 onward uses DFX terminology.
This guide includes the following information:
- A description of DFX as implemented in the AMD Vivado™ Design Suite.
- An assumption of familiarity with FPGA design software, especially the Vivado Design Suite.
DFX supports the following products. For a complete list of supported devices, see Supported Devices.
-
7 series devices
- DFX supports nearly all AMD Virtex™ 7, AMD Kintex™ 7,
AMD Artix™ 7,
and AMD Zynq™ 7000 SoC devices.Note: DFX does not support AMD Spartan™ 7 devices, Artix 7 A12T, and 7A25T devices.
- DFX supports nearly all AMD Virtex™ 7, AMD Kintex™ 7,
AMD Artix™ 7,
and AMD Zynq™ 7000 SoC devices.
-
AMD UltraScale™
devices
- Place and route, and bitstream generation is enabled for all
production devices.Note: Expect higher memory usage on VU440 devices than on other devices. Memory usage can exceed 64 MB.
- Bitstream generation is disabled by default for ES2 devices, but place and route can still be performed.
- Place and route, and bitstream generation is enabled for all
production devices.
-
AMD UltraScale+™
devices
- You can run place and route and generate bitstreams for all production devices across all families. Artix UltraScale+, Kintex UltraScale+ Virtex UltraScale+ and Spartan UltraScale+. Zynq UltraScale+ MPSoC and RFSoC devices are also supported.
- You can run place and route on many engineering silicon (ES1, ES2) versions of UltraScale+ devices. Bitstream generation is disabled by default on these devices.
-
AMD Versal™
devices
- You can use production DFX support on all Prime, AI Core, Premium, AI Edge, and HBM devices. See the device support table in Supported Devices for the complete list.
- Some Versal devices are available in ES1 silicon. These devices are limited early access with license-gated implementation and parameter-gated device image generation. Contact AMD support if access to any of these devices are needed.