Insertion - 2024.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-12-13
Version
2024.2 English

When using insertion, signals are identified in the block design or RTL source, and insertion of the ILA debug core is done later in the flow. To add a debug tag to a signal on a block design canvas, right-click and select Debug, as shown in the following figure.

Figure 1. Insertion Example Before

After you select Debug, the green bug icon is added to the signal, as shown in the following figure.

Figure 2. Insertion Example After

In the Tcl Console, this action appears as adding the DEBUG property to that net:

set_property HDL_ATTRIBUTE.DEBUG true [get_bd_nets {c_counter_binary_0_Q}]
The equivalent process within RTL is done using the MARK_DEBUG attribute. When RTL code that uses this attribute is added to a block design as a module reference, and the Debug Hub IP has been added, the same insertion technique is used. Here is the attribute applied in Verilog:
(* mark_debug = "true" *) reg [31:0] count_out;
Note: In each of these cases, the Debug Hub IP (green) was explicitly added to the BD canvas and connected to the NoC.