Edge-triggered Resets - 2025.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2025-12-17
Version
2025.2 English

Some blocks in an RM can be sensitive to a specific edge of the reset signal, either to perform their own reset or to trigger operation. For example, a watchdog counter designed to ensure that the reset phase exits might reset itself on the transition of an active-High reset from 0 to 1, and then count while reset remains at 1.

If your RM contains such a block, you must assume it can become corrupted from the moment GWE asserts until it sees the required reset edge. During this time, you should isolate it from the rest of the RM by using DFX decouplers to limit any potential corruption. You can assume the remainder of the RM is held in reset with safe initial values, making corruption of the block from the RM unlikely, but isolating its inputs with decouplers is still a wise precaution.

The safest way to handle a block like this, in addition to the decoupling described earlier, is to route a dedicated reset to it. While you hold the remainder of the RM in reset with an active-level reset, you can pulse the dedicated reset for the edge-triggered block. This limits the chances of the edge-triggered block corrupting the remainder of the RM. With careful timing, you can align the active edge of the reset signal with the deassertion of the level-based reset, allowing all parts of the RM to start operating on the same clock edge.

Block A has an active-High level-base reset. Block B has an edge-triggered reset, sensitive to the rising edge.

Figure 1. Using Multiple Reset Signals to Handle Level and Edge Sensitive Resets in an RM

The problems here are in:

  • Phase 1, where block B might be corrupted.
  • Phase 2, where block B might remain corrupted depending on the efficacy of the reset.

Another way to handle this is to use a single reset signal for all parts of the RM. In this case, you need to hold reset asserted until you see EOS, and then pulse it to generate the edge required by the edge-triggered block. The edge-triggered block can become corrupted from the assertion of GWE until it detects the active reset edge. This approach assumes the reset can fully restore the block’s state.

Block A has an active-High level-base reset. Block B has an edge-triggered reset, sensitive to the rising edge.

Figure 2. Using a Single Reset Signal to Handle Level and Edge Sensitive Resets in an RM

The problems here are in:

  • Phase 1, where block B is corrupted.
  • Phase 2, where block A is active and block B is corrupted.
  • Phase 3, where block B might remain corrupted depending on the efficacy of the reset.

The two-reset approach is superior, although much depends on your reset’s ability to bring the block into a known good state. For example, it should be able to repair possibly corrupted memory entries.

In both cases, parts of the RM can become corrupted, and all you can do is try to limit the extent of any infection.