MBUFG primitives in Versal devices allow clock division at the leaf level to reduce clock track utilization and improve timing closure on synchronous CDCs. For DFX designs, MBUFG optimization is allowed only for static clock nets, internal RM clock nets, or usage of only the undivided O1 output at the RP boundary. The O1 clock output from a static MBUFG can drive loads in one or more dynamic regions. Boundary clock nets can continue to use BUFGCE_DIV/MMCM/PLL clocking primitives for clock division. However, this will have reduced QoR benefits compared to using MBUFG primitives because the latter provides common clock node closer to loads at the leaf level. Therefore, it is recommended to use MMCM/PLL inside partitions of the DFX design to convert a boundary clock net to an internal clock net that can leverage the full set of MBUFG optimizations of the Vivado tools. The CLRB_LEAF input on the MBUFG primitives is used to asynchronously reset the BUFDIV_LEAF dividers. There are cases where special handling is required to ensure that BUFDIV_LEAF dividers are reset to their startup state. If the clock modifying that drives the MBUFG is reset in between the operation, the MBUFG output clocks should also be reset to get synchronized. If divided output clocks from an MBUFG in static drive inputs to Reconfigurable Partitions, the following error will occur:
ERROR: [DRC HDPR-99] Versal Illegal MBUFGxx drivers in pblock: Reconfigurable Pblock ‘<pblock_name>' contains a MBUFGxx boundary clock net driver ‘<MBUFG Driver Name>'