Versal devices support partial reconfiguration for almost all component types. Logic that can be placed in an RM includes:
- NoC master units (NMUs) and NoC slave units (NSUs)
- Boundary logic interface (BLI) flip-flops
- XPIO and HDIO banks, including XPHY, ISERDES, OSERDES, and IDELAYCTRL
- Memory controllers: DDRMC and DDRMC_RIU
- Serial transceivers (MGTs) and related components: GTYE5_QUAD, MRMAC, PCIE40E5, and GTM_DUAL
- All logic components that are mapped to a CLB slice, including LUTs (look-up tables), LUTRAMs, FFs (flip-flops), SRLs (shift registers), and LOOKAHEAD.
- Block RAM: RAMB18E5 and RAMB36E5
- DSP blocks: DSP48E2
- High-speed channelized cryptography engines (HSC)
- PCIe® (PCI Express), CMAC (100G MAC), and ILKN (Interlaken MAC) blocks
- UltraRAM blocks: URAM288E5 and URAM288E5_BASE
- Clocks and clock modifying logic, including BUFG_FABRIC, BUFGCE, BUFG_GT, BUFG_GT_SYNC, BUFGMUX, MMCM, DPLL, XPLL, and MBUFG
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AI Engines
Note: Versal AI Engine inclusion in RMs is supported through Vitis platform flows only.