Design Compatibility Checks in Versal Hardware - Design Compatibility Checks in Versal Hardware - 2026.1 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2026-07-01
Version
2026.1 English

In the previous section, 32-bit unique identifiers (UIDs) are embedded in each PDI. The PLM uses these UIDs to validate incoming programming images. These checks apply to both Segmented Configuration and DFX. PLM validates each image delivered to the PMC against the currently loaded design.

Node IDs are assigned as follows:

  • The segmented boot PDI always uses node ID 0x18700000
  • The segmented PLD PDI always uses node ID 0x18700001
  • DFX partial PDIs start at node ID 0x18700002 and increment for each additional RP in the design

When both Segmented Configuration and DFX are enabled in a design:

  • The segmented boot PDI has a UID generated by Vivado and a parent ID of 0
  • The segmented PLD PDI has a UID generated by Vivado and a parent ID that matches the boot PDI UID
  • Each DFX partial PDI has a UID generated by Vivado and a parent ID that matches the PLD PDI UID

If the parent ID of an incoming PDI does not match the UID of the resident node above it, PLM reports a failure, and it does not load the PDI.