Design Clock Utilization Summary - 2024.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-12-13
Version
2024.2 English

The Design Clock Utilization Summary shows the summary of global clocks used in the design. The table gives clock net names and related details. The table includes clock information for both static and dynamic domains of the design.

Note: For more information about clock usage, use the report_clock_utilization Tcl command.
Table 1. Design Clock Utilization Summary
Column Description
Clock Source Clock source in static domain or RP
Driver Type / Pin Output primitive pin that generates the clock
Driver Clock Region Device clock region where the clock source is located
Clock Track Clock track ID is used to route the clock net
Clock Expansion Window Rectangular area that includes all clock regions where clock net loads are placed
Clock Root Clock region where the clock net CLOCK_ROOT is located
Clock Period Period in nanoseconds of timing clock that propagates on the clock net
Static Load Numbers Number of static cells connected to clock driver pin
RP Load Numbers Number of RP cells connected to clock driver pin (one column per RP)
Net Name Logical name of clock net segment connected to the clock driver pin
Figure 1. Design Clock Utilization Summary Table