AMD Vivado™ uses the Advanced Flow architecture for Versal devices. The Advanced Flow provides place and route features designed to improve compile time and performance through more advanced technologies and parallelization techniques. When targeting Versal technologies, the Advanced Flow is always run. 7 series and AMD UltraScale™ architectures do not use the Advanced Flow.
Versal DFX designs created before 2024.2 can be migrated to the Advanced Flow. Upgrading such designs requires more consideration than a typical Vivado version upgrade because of the implementation flow change. You might choose not to migrate designs that are already in production, designs nearing completion, designs for which significant timing-closure effort has already been invested, or designs that depend on features such as Intelligent Design Runs that are not supported by Advanced Flow.
One limitation that makes upgrades from pre-2024.2 releases more restrictive is that placement and routing data cannot be migrated because the Advanced Flow uses different internal data structures than earlier releases. This means any pre-2024.2 design that has run past the Place Design step is incompatible with Vivado post-2024.2. Therefore, platforms released prior to 2024.2 cannot be imported into current versions of Vivado to update reconfigurable modules or create new ones.
pr_verify utility flags errors if this
is attempted.For Vivado projects, automatic migration occurs when the project is opened in Vivado 2024.2 or later. The migration process updates the project's implementation runs so that only Advanced Flow-supported commands are used. After a Versal project has been migrated to Advanced Flow, it cannot be opened in earlier Vivado versions. Therefore, AMD strongly recommends backing up the project under revision control before migration. For non-project users, minor script modifications are required.
After migration, rerun all parent and child configuration runs to establish a new static design image and a new collection of reconfigurable modules. For most designs, synthesis does not need to be rerun. The exception is designs with a single reconfigurable partition targeting devices that use SSI Technology; in these cases, synthesis must also be rerun to ensure the correct NoC data is established and propagated through the flow.
After migration, review implementation results carefully to determine whether additional adjustments are needed. One expected change is in Reconfigurable Partition Pblock handling: the base Pblock snaps outward to include all covered programmable units rather than inward, which can cause more resources to be identified as dynamic instead of static. In some cases, this can create unroutable conditions if the static design no longer retains the resources needed to complete routing.
For more information on the Advanced Flow, refer to Vivado Design Suite User Guide: Implementation (UG904) and Answer Record 000036830.