For DFX designs with two or more Reconfigurable Partitions, clock buffers can be blocked from use if two RP footprints expand to both cover the same resources. In the following floorplan, both RP (rp1rm1 shown in blue and rp2rm1 shown in yellow) occupy space in the X9 column (the farthest clock region on the right). Clock region X9Y2 is legally shared between the two partitions.
When routing expansion obtains BUFG_GT resources, both try to collect the sites along the right side of the chip. The following image shows the expanded routing footprint of pblock_rp1rm1, which includes sites within the pblock_rp2rm1 area.
Two independent RPs cannot both own the same resources. Any sites that
are in conflict are marked with a PROHIBIT property so neither RP is able to use them.
DFX and Floorplanning DRCs do not currently flag this condition. The only indication
that this conflict exists is the existence of prohibited locations after opt_design. In general this does not lead to an error,
unless the reduced set of clocking resources are insufficient to implement the
design.
To resolve this resource overlap, adjust the blue Pblock to avoid the clock regions in the X9 column. The yellow Pblock then has sole ownership of the BUFG_GTs on the right side of the chip. The shared X9Y2 clock region is irrelevant. Even if the blue Pblock does not include this clock region but does occupy clock regions above (for example, X9Y3) the same resource usage would be requested.