Access to End of Startup (EOS) - 2025.2 English - UG909

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
Document ID
UG909
Release Date
2025-12-17
Version
2025.2 English

You must keep an RM isolated while partial reconfiguration is occurring. After you complete the full reconfiguration event, including the dedicated initialization, you can release the decoupling. Your configuration management solution or embedded software can control the release of decoupling by sending a signal to the PL when ready. You can also use the end of startup (EOS) pin to drive the release, which indicates when configuration events have completed.

In AMD UltraScale™ and AMD UltraScale+™ devices, the EOS pin is located on the STARTUP block. Instantiate the STARTUPE3 primitive and connect the EOS pin to the control logic that releases decoupling in your design.

Figure 1. STARTUPE3 Primitive
In first-generation Versal devices, you can access the EOS signal from the CIPS IP, but you cannot select it from the customization GUI. You must enable the pin in Tcl using the following command:
set_property CONFIG.PS_PMC_CONFIG(PS_USE_STARTUP) {1} \
           [get_bd_cells versal_cips_0]
Note: Modify veral_cips_0 to match the name in your design.
In second generation Versal devices that use the PS Wizard IP for AMD Versal™ AI Edge Series Gen 2, AMD Versal™ Prime Series Gen 2, and AMD Versal Premium Series Gen 2 devices, the syntax is similar, with only the IP reference changed:
set_property CONFIG.PS11_CONFIG(PS_USE_STARTUP) {1} \
           [get_bd_cells versal2_ps_wizard_0]
Note: Modify versal2_ps_wizard_0 to match the name in your design.
Figure 2. EOS Pin Enabled on the CIPS IP

After you expose the EOS pin, connect it to the control logic that releases decoupling in your design.